<<
false sharing
FE_BUBBLE
FE_LOST_BW
FIFO Buffer
first-level cache load misses
floating point
and integer instructions cannot pair
assist (micro-code)
assist performance impact
computation instructions
computational operations executed
operations retired
flushes
FP_FAILED_FCHKF
FP_FALSE_SIRSTALL
FP_FLUSH_TO_ZERO
FP_OPS_RETIRED
FP_TRUE_SIRSTALL
front-end
full sized read invalidate bus utilization
fused
events for Intel(R) Pentium(R) M processors
hardware interrupts received
HPW_DATA_REFERENCES
HT technology
Hyper-Threading technology
IA32_INST_RETIRED
IA32_IPC
IA32_ISA_TRANSITIONS
IA64_INST_RETIRED
IA64_IPC
IA64_TAGGED_INST_RETIRED
IDEAL_BE_LOST_BW_DUE_TO_FE
immediate operand and address displacement
INST_CHKA_LDC_ALAT
INST_DISPERSED
INST_FAILED_CHKA_LDC_ALAT
INST_FAILED_CHKS_RETIRED
instruction
decoded
not executed
Intel NetBurst(R) microarchitecture
Intel SpeedStep(R) technology
events for Intel(R) Pentium(R) M processors
Intel(R) processor information on the web
ISB_BUNPAIRS_IN
ISB_LINES_IN
ITLB page walk misses
ITLB_MISSES_FETCH
L1 cacheable
data reads
data reads and writes
data writes
lock reads
L1D_READS_SET0
L1D_READS_SET1
L1DTLB_EAR_EVENTS
L1DTLB_FOR_L1D_MISS_RATIO
L1DTLB_REFERENCES
L1DTLB_TRANSFER
L1I_DEMAND_MISS_RATIO
L1I_EAR_EVENTS
L1I_FETCH_ISB_HIT
L1I_FETCH_RAB_HIT
L1I_FILLS
L1I_MISS_RATIO
L1I_PREFETCH_MISS_RATIO
L1I_PREFETCHES
L1I_PURGE
L1I_PVAB_OVERFLOW
L1I_RAB_ALMOST_FULL
L1I_RAB_FULL
L1I_READS
L1I_REFERENCES
L1I_SNOOP
L1I_STRM_PREFETCHES
L1ITLB_EAR_EVENTS
L1ITLB_INSERTS_HPW
L1ITLB_MISS_RATIO
L1ITLB_REFERENCES
l2 address strobes=> address bus utilization
l2 bus busy loading data
l2 cache
instruction fetch misses
l2 instruction fetches
l2 miss performance impact
l2 read misses
l2 reads
l2 requests
l2 write misses
l2 writes
L2_BAD_LINES_SELECTED
L2_BYPASS
L2_DATA_RATIO
L2_DATA_READS
L2_DATA_REFERENCES
L2_DATA_WRITES
L2_FORCE_RECIRC
L2_GOT_RECIRC_IFETCH
L2_GOT_RECIRC_OZQ_ACC
L2_IFET_CANCELS
L2_INST_DEMAND_READS
L2_INST_FETCHES
L2_INST_PREFETCHES
L2_INST_REFERENCES
L2_ISSUED_RECIRC_IFETCH
L2_ISSUED_RECIRC_OZQ_ACC
L2_L3ACCESS_CANCEL
L2_LINES_IN
L2_LINES_OUT
L2_M_LINES_OUT
L2_MISS_RATIO
L2_MISSES
L2_OPS_ISSUED
L2_OZDB_FULL
L2_OZQ_ACQUIRE
L2_OZQ_CANCELS1
L2_OZQ_CANCELS2
L2_OZQ_FULL
L2_OZQ_RELEASE
L2_RECIRC_ATTEMPTS
L2_REFERENCES
L2_REQUESTS
L2_STORE_HIT_SHARED
L2_SYNTH_PROBE
L2_VICTIMB_FULL
L2_WB_HITS
L2_WB_MISSES
L2_WB_REFERENCES
L2DTLB_MISS_RATIO0
L2DTLB_MISS_RATIO1
L2DTLB_MISSES
L3_DATA_HITS
L3_DATA_MISS_RATIO
L3_DATA_READ_MISSES
L3_DATA_READ_RATIO
L3_DATA_READ_REFERENCES
L3_INST_HITS
L3_INST_MISS_RATIO
L3_INST_MISSES
L3_INST_RATIO
L3_INST_REFERENCES
L3_LINES_REPLACED
L3_MISS_RATIO
L3_MISSES
L3_READ_HITS
L3_READ_MISSES
L3_READ_REFERENCES
L3_READS
L3_REFERENCES
L3_STORE_HITS
L3_STORE_MISSES
L3_STORE_REFERENCES
L3_WRITE_HITS
L3_WRITE_MISSES
L3_WRITE_REFERENCES
L3_WRITES
label
latency
long
LD_BLOCKS
leave
load port
Loads Blocked
LOADS_RETIRED
long instruction pairing restriction
loop unrolling
m-state
events for Intel(R) Pentium(R) M processors
machine clear count
MEM_READ_CURRENT
memory
accesses
operands
micro-op
decoder added
micro-ops delivered to queue
from the microcode rom
while in build mode
while in deliver mode
micro-ops retired
low parallelization
misaligned data memory reference
MISALIGNED_LOADS_RETIRED
MISALIGNED_STORES_RETIRED
mispredicted branches
events for Intel(R) Pentium(R) M processors
mispredicted indirect calls
instructions executed
performance impact
MMX(TM) technology
arithmetic instructions
instructions
logic instructions
multiply instructions
operations
shift instructions
unpack operations
MOB
more measurements
motion
nominal system cpi
non-halted CPI
non-halted system CPI
non-prefetch bus accesses
NOPS_RETIRED
P6 family microarchitecture
partial stall
partial wc memory transactions
penalties
for Intel(R) Itanium(R) 2 processor
for Intel(R) Pentium(R) 4 processor
for Intel(R) Pentium(R) M processor
Pentium(R) 4 processor
Pentium(R) M processor
advice
event ratios
events
penalties
percentage prefetches
PGBO
pipeline clears
from memory ordering issues
from self-modifying code
poor code locality
PREDICATE_SQUASHED_RETIRED
prefetch
events for Intel(R) Pentium(R) M processors
penalties
percentage
PRM (Programer's Reference Manual)
processor events
for Intel(R) Pentium(R) M processors
profile guided basic-block optimization
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