ITLB Page Walk Misses

This number represents the estimated impact from page walk requests due to ITLB (Instruction Translation Lookaside Buffer) misses. When a 32-bit linear instruction address is submitted by the processor, it is first submitted to the linear addressed instruction cache (trace cache). Upon a trace cache miss the address is submitted to ITLB. The translation lookaside buffer (TLB) translates the resulting 32-bit linear address into a 36-bit physical memory address before the cache lookup is performed. ITLB size and organization are processor design-specific. An ITLB miss requires memory accesses to the OS page directory and tables in order translate the 32-bit linear address. This event counts the number of requests for a page walk due to a ITLB miss. A page walk is the traversing of the OS page tables by the hardware in order to translate the 32-bit linear address. A miss by the page walk results in a page fault so that OS can load the necessary page into the tables. A ITLB miss does not necessarily indicate a cache miss.

For systems with the Hyper-Threading Technology enabled or multi-processor systems, the estimated impact represents the total processor time impact (added across all logical/physical processors on the system), and not the "wall-clock" time impact. Therefore, on a system with the Hyper-Threading Technology enabled or multi-processor system, it is quite possible to see an insight having an impact greater than the workload wall-clock run time. Note that on a UP system, processor time is the same as wall-clock time.

Counter dependencies:

This insight is dependent on the following performance counter function:

PageWalkMissITLB = ((ITLB Page Walks (TI)*30)/Clockticks)*100
low value: 0.2
high value: 2

This insight is relevant when PageWalkMissITLB is high.

Advice:

Avoiding ITLB Page Walk Misses