The Intel NetBurst(R) microarchitecture provides the following important features:
Rapid Execution Engine:
Arithmetic Logic Units (ALUs) run at twice the processor frequency.
Basic integer operations executes in 1/2 processor clock tick.
Provides higher throughput and reduced latency of execution.
Hyper Pipelined Technology:
Twenty-stage pipeline to enable industry-leading clock rates for desktop PCs and servers.
Provides frequency headroom and scalability to continue leadership into the future.
Advanced Dynamic Execution:
Very deep, out-of-order, speculative execution engine.
Up to 126 instructions in flight.
Up to 48 loads and 24 stores in pipeline.
Enhanced branch prediction capability.
Reduces the mis-prediction penalty associated with deeper pipelines.
Advanced branch prediction algorithm.
4K-entry branch target array.
New cache subsystem:
First-level caches.
Advanced Execution Trace Cache stores decoded instructions.
Execution Trace Cache removes decoder latency from main execution loops.
Execution Trace Cache integrates path of program execution flow into a single line.
Low latency data cache with 2 cycle latency.
second level cache.
Full-speed, unified 8-way 2nd-Level on-die Advance Transfer Cache.
Bandwidth and performance increases with processor frequency.
High-performance, quad-pumped bus interface to the Intel NetBurst microarchitecture system bus.
Support quad-pumped, scalable bus clock to achieve 4X effective speed.
Capable of delivering up to 3.2 GB of bandwidth per second for Pentium(R) 4 processor.
Superscalar issue to enable parallelism.
Expanded hardware registers with renaming to avoid register name space limitations.
128-byte cache line size.
Two 64-byte sectors.
Illustration: The Intel NetBurst Microarchitecture
This microarchitecture pipeline is made up of three sections: an in-order issue front end, an out-of-order superscalar execution core, and an in-order retirement unit. For an overview of each of these pipeline sections, see the IA-32 Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture. See Intel(R) Processor Information on the Web for more details.