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Qxi

rdtsc--read time-stamp counter
read
read bus utilization
reduce
    cache misses
    events that cause TC flushes
    partial write-combining (WC) transactions
    uncacheable transactions
resource related stalls
retired branch instructions
RSE_AVG_CURRENT_REGS
RSE_AVG_DIRTY_REGS
RSE_AVG_INVALID_REGS
RSE_AVG_LOAD_LATENCY
RSE_CURRENT_REGS
RSE_CURRENT_REGS_2_TO_0
RSE_CURRENT_REGS_5_TO_3
RSE_CURRENT_REGS_6
RSE_DIRTY_REGS
RSE_DIRTY_REGS_2_TO_0
RSE_DIRTY_REGS_5_TO_3
RSE_DIRTY_REGS_6
RSE_EVENT_RETIRED
RSE_LOAD_LATENCY_PENALTY
RSE_REFERENCES_RETIRED

saturated arithmetic instructions executed
second-level cache load misses
segment
    register loads
    rename stalls - DS
    rename stalls - ES DS FS GS
    rename stalls - FS
    rename stalls - GS
    renames - DS
    renames - ES
    renames - ES DS FS GS
    renames - FS
    renames - GS
self modifying code
    clear
    clear performance impact
    detected
SERIALIZATION_EVENTS
show
    indications
SIMD assists
speculative execution efficiency
split
    loads performance impact
    store replays event
    stores performance impact
SSE
    events for Intel(R) Pentium(R) M processors
SSE2
    events for Intel(R) Pentium(R) M processors
stalled cycles of store buffer resources (non-standard)
stalls of store buffer resources (non-standard)
    bank conflict
    fisttp
    latency
    monitor
    mwait
    pause
    possible spin loop
    possible_inefficient_conversion warning
    SSE3 warnings
    stall
        static assembly penalties
store buffer
    block
    drain cycles
store forward performance impact
STORES_RETIRED
Streaming SIMD Extensions
    events for Intel(R) Pentium(R) M processors
    input assists per instructions retired
    input assists performance impact
    instructions
    prefetch NTA instructions executed
    prefetch T1 instructions executed
    prefetch T2 instructions executed
Streaming SIMD Extensions 2
    events for Intel(R) Pentium(R) M processors
Streaming SIMD Extensions 2 (SSE2)
    computational instructions
Streaming SIMD Extentions
    computational instructions
    input assists
SYLL_NOT_DISPERSED
SYLL_OVERCOUNT

tagged mispredicted branches retired
taken branch
    mispredictions
    retired
tc flushes
thermal trip
thread
thread independent
TI (thread independent)
TLB (translation lookaside buffer)
    events for Pentium(R) 4 processors
total instruction fetches
    misses
trace cache
    delivery performance
trace cache delivery rate
trace cache flushes
trace cache misses
    decrease
    performance impact
transitions
    from floating-point to MMX(TM) instructions
    from MMX(TM) instructions to FP instructions
TS (thread specific)
TS-E (thread specific ESCR restricted)
two branches

U pipe
UC_LOADS_RETIRED
UC_STORES_RETIRED
uncacheable memory transactions
uops
    retired
upward
user-defined event ratio

V and U pipes

write
    bus utilization
    combining
    combining buffer (WCB) full evictions

x87 input assists
    performance impact
x87 output assists
    performance impact