Tip Thread Specificity: TS
The number of page walk requests due to instruction translation lookaside buffer (ITLB) misses. When a 32-bit linear instruction address is submitted by the processor, it is first submitted to the linear addressed instruction cache (trace cache). Upon a trace cache miss the address is submitted to ITLB. The translation lookaside buffer (TLB) translates the resulting 32-bit linear address into a 36-bit physical memory address before the cache lookup is performed. ITLB size and organization are processor design-specific. An ITLB miss requires memory accesses to the OS page directory and tables in order translate the 32-bit linear address. This event counts the number of requests for a page walk due to a ITLB miss. A page walk is the traversing of the OS page tables by the hardware in order to translate the 32-bit linear address. A miss by the page walk results in a page fault so that OS can load the necessary page into the tables. A ITLB miss does not necessarily indicate a cache miss.
Tip To minimize ITLB misses:
Make sure your application has good code locality.
Try to minimize the size of the source code and locality so that instructions span a minimum number of pages, and so that the instruction span is less then the number of ITLB entries.