Operation |
Mnemonic(s) |
|---|---|
|
Ordered load and ordered check load |
|
|
Ordered Store |
|
|
Exchange memory and general register |
|
|
Conditional exchange of memory and general register |
|
|
Add immediate to memory |
|
|
Memory ordering fence |
For details, see Volume 3: Instruction Set Reference of the Intel(R) Itanium(R) Architecture Software Developer's Manual . For the latest updates on the instruction set information, go to the web site.