xchg
Instruction Type M
Format
(qp) xchgsz.ldhint r1 = [r3], r2
Description
A value consisting of sz bytes is read from memory starting at the address specified by the value in GR r3. The least significant sz bytes of the value in GR r2 are written to memory starting at the address specified by the value in GR r3. The value read from memory is then zero extended and placed in GR r1 and the NaT bit corresponding to GR r1 is cleared.
If the address specified by the value in GR r3 is not naturally aligned to the size of the value being accessed in memory, an Unaligned Data Reference fault is taken independent of the state of the User Mask alignment checking bit, UM.ac (PSR.ac in the Processor Status Register).
Both read and write access privileges for the referenced page are required.
The exchange is performed with acquire semantics, i.e. the memory read/write is made visible prior to all subsequent data memory accesses.
The memory read and write are guaranteed to be atomic.
This instruction is only supported to cacheable pages with write-back write policy. Accesses to NaTPages cause a Data NaT Page Consumption fault. Accesses to pages with other memory attributes cause an Unsupported Data Reference fault.
The value of the ldhint completer specifies the locality of the memory access. Locality hints do not affect program functionality and may be ignored by the implementation.
For details, see Volume 3: Instruction Set Reference of the Intel(R) Itanium(R) Architecture Software Developer's Manual . For the latest updates on the instruction set information, go to the web site.