cmpxchg - Compare and Exchange Instruction

cmpxchg

Operation Font Conventions

Instruction Type M

Format

(qp) cmpxchgsz.sem.ldhint r1 = [r3], r2, ar.ccv


Description

A value consisting of sz bytes is read from memory starting at the address specified by the value in GR r3. The value is zero extended and compared with the contents of the cmpxchg Compare Value application register (ARCCV]). If the two are equal, then the least significant sz bytes of the value in GR r2 are written to memory starting at the address specified by the value in GR r3. The zero-extended value read from memory is placed in GR r1 and the NaT bit corresponding to GR r1 is cleared.

The values of the sz completer are in the Memory Compare and Exchange Size table. The sem completer specifies the type of semaphore operation. These operations are described in the Compare and Exchange Semaphore Types table.

If the address specified by the value in GR r3 is not naturally aligned to the size of the value being accessed in memory, an Unaligned Data Reference fault is taken independent of the state of the User Mask alignment checking bit, UM.ac (PSR.ac in the Processor Status Register).

The memory read and write are guaranteed to be atomic.

Both read and write access privileges for the referenced page are required. The write access privilege check is performed whether or not the memory write is performed.

This instruction is only supported to cacheable pages with write-back write policy. Accesses to NaTPages cause a Data NaT Page Consumption fault. Accesses to pages with other memory attributes cause a Unsupported Data Reference fault.

The value of the ldhint completer specifies the locality of the memory access. The values of the ldhint completer are given in the Load Hints table. Locality hints do not affect program functionality and may be ignored by the implementation. See ”Memory Hierarchy Control and Consistency” on page 4-17 for details.


 

 

 

 

 

 

 


For details, see Volume 3: Instruction Set Reference of the Intel(R) Itanium(R) Architecture Software Developer's Manual . For the latest updates on the instruction set information, go to the web site.