CMPPS--Compare Packed Single-Precision Floating-Point Values

Description

Performs a SIMD compare of the four packed single-precision floating-point numbers in the source operand (second operand) and the destination operand (first operand) and returns the results of the comparison to the destination operand. The comparison predicate operand (third operand) specifies the type of comparison performed on each of the pairs of packed values. The comparison result is four doubleword masks of all 1s (comparison true) or all 0s (comparison false). The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The comparison predicate operand is an 8-bit immediate the first 3 bits of which define the type of comparison to be made (see Comparison Predicate for CMPPD and CMPPS Instructions); bits 4 through 7 of the immediate are reserved.

A subsequent computational instruction that uses the mask result in the destination operand as an input operand will not generate a fault, since a mask of all 0s corresponds to a floating-point number of +0.0 and a mask of all 1s corresponds to a QNaN floating-point number.

Some of the comparisons (such as the greater-than, greater-than-or-equal, not-greater-than, and not-greater-than-or-equal relations) can be achieved only through software emulation. For these comparisons the programmer must swap the operands, copying registers when necessary to protect the data that will now be in the destination, and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in under the heading Emulation.

Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPPS instruction:

The greater-than relations not implemented in hardware require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.)

Operation

CASE (COMPARISON PREDICATE) OF
0: OP EQ;
1: OP LT;
2: OP LE;
3: OP UNORD;
4: OP NE;
5: OP NLT;
6: OP NLE;
7: OP ORD;
EASC
CMP0 DEST[31-0] OP SRC[31-0];
CMP1 DEST[63-32] OP SRC[63-32];
CMP2 DEST [95-64] OP SRC[95-64];
CMP3 DEST[127-96] OP SRC[127-96];
IF CMP0 == TRUE
THEN DEST[31-0] FFFFFFFFH
ELSE DEST[31-0] 00000000H; FI;
IF CMP1 == TRUE
THEN DEST[63-32] FFFFFFFFH
ELSE DEST[63-32] 00000000H; FI;
IF CMP2 == TRUE
THEN DEST95-64] FFFFFFFFH
ELSE DEST[95-64] 00000000H; FI;
IF CMP3 == TRUE
THEN DEST[127-96] FFFFFFFFH
ELSE DEST[127-96] 00000000H; FI;

Intel(R) C++ Compiler Intrinsic Equivalents

CMPPS for equality __m128 _mm_cmpeq_ps(__m128 a, __m128 b)

CMPPS for less-than __m128 _mm_cmplt_ps(__m128 a, __m128 b)

CMPPS for less-than-or-equal __m128 _mm_cmple_ps(__m128 a, __m128 b)

CMPPS for greater-than __m128 _mm_cmpgt_ps(__m128 a, __m128 b)

CMPPS for greater-than-or-equal __m128 _mm_cmpge_ps(__m128 a, __m128 b)

CMPPS for inequality __m128 _mm_cmpneq_ps(__m128 a, __m128 b)

CMPPS for not-less-than __m128 _mm_cmpnlt_ps(__m128 a, __m128 b)

CMPPS for not-greater-than __m128 _mm_cmpngt_ps(__m128 a, __m128 b)

CMPPS for not-greater-than-or-equal __m128 _mm_cmpnge_ps(__m128 a, __m128 b)

CMPPS for ordered __m128 _mm_cmpord_ps(__m128 a, __m128 b)

CMPPS for unordered __m128 _mm_cmpunord_ps(__m128 a, __m128 b)

CMPPS for not-less-than-or-equal __m128 _mm_cmpnle_ps(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

Invalid, if SNaN operands, Denormal.

Protected Mode Exceptions

#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If memory operand is not aligned on a 16-byte boundary, regardless of segment.

#SS(0) - For an illegal address in the SS segment.

#PF(fault-code) - For a page fault.

#NM - If TS in CR0 is set.

#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.

Real-Address Mode Exceptions

#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment Interrupt 13. If any part of the operand lies outside the effective address space from 0 to 0FFFFH.

#NM - If TS in CR0 is set.

#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#PF(fault-code) - For a page fault.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.