Opcode |
Instruction |
Description |
|---|---|---|
|
0F AE /7 |
CLFLUSH m8 |
Flushes cache line containing m8. |
Invalidates the cache line that contains the linear address specified with the source operand from all levels of the processor cache hierarchy (data and instruction). The invalidation is broadcast throughout the cache coherence domain. If, at any level of the cache hierarchy, the line is inconsistent with memory (dirty) it is written to memory before invalidation. The source operand is a byte memory location.
The availability of the CLFLUSH is indicated by the presence of the CPUID feature flag CLFSH (see CPUID--CPU Identification). The aligned cache line size affected is also indicated with the CPUID instruction.
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It should be noted that processors are free to speculative fetch and cache data from system memory regions assigned a memory-type allowing for speculative reads (i.e. WB, WC, WT memory types). The Streaming SIMD Extensions PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not tied to instruction execution, CLFLUSH is not ordered with respect to PREFETCHh or any of the speculative fetching mechanisms (that is, data could be speculative loaded into the cache just before, during, or after the execution of a CLFLUSH to that cache line).
CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed to be ordered by any other fencing, serializing or other CLFLUSH instruction. For example, software can use an MFENCE instruction to insure that previous stores are included in the write-back.
The CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking and faults associated with a byte load except a CLFLUSH is allowed to an execute-only segment. Like a load, the CLFLUSH instruction sets the A bit but not the D bit in the page tables.
Flush_Cache_Line(SRC)
CLFLUSH void_mm_clflush(void const *p)
#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0) - For an illegal address in the SS segment.
#PF(fault-code) - For a page fault.
#UD - If CPUID feature flag CLFSH is 0.
Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.
#UD - If CPUID feature flag CLFSH is 0. If CPUID feature flag SSE2 is 0.
Same exceptions as in Real Address Mode.
#PF(fault-code) - For a page fault.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.