CPUID--CPU Identification

Description

Provides processor identification information in registers EAX, EBX, ECX, and EDX. This information identifies Intel as the vendor, gives the family, model, and stepping of processor, feature information, and cache information. An input value loaded into the EAX register determines what information is returned, as shown in the following table:

Information Returned by CPUID Instruction

The ID flag (bit 21) in the E

FLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction.

The information returned with the CPUID instruction is divided into two groups: basic information and extended function information. Basic information is returned by entering an input value of from 0 to 3 in the EAX register depending on the IA-32 processor type; extended function information is returned by entering an input value of from 80000000H to 80000004H. The extended function CPUID information was introduced in the Pentium(R) 4 processor and is not available in earlier IA-32 processors. The table "Highest CPUID Source Operand for IA-32 Processors" shows the maximum input value that the processor recognizes for the CPUID instruction for basic information and for extended function information, for each family of IA-32 processors on which the CPUID instruction is implemented.

Highest CPUID Source Operand for IA-32 Processors

If a higher value than is shown in "Information Returned by CPUID Instruction" is entered for a particular processor, the information for the highest useful basic information value is returned. For example, if an input value of 5 is entered in EAX for a Pentium 4 processor, the information for an input value of 2 is returned. The exception to this rule is the input values that return extended function information (currently, the values 80000000H through 80000004H). For a Pentium 4 processor, entering an input value of 80000005H or above, returns the information for an input value of 2.

The CPUID instruction can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed (see Serializing Instructions in Chapter 7 of the IA-32 Intel(R) Architecture Software Developer's Manual, Volume 3).

When the input value in the EAX register is 0, the processor returns the highest value the CPUID instruction recognizes in the EAX register for returning basic CPUID information (see the table "Highest CPUID Source Operand for IA-32 Processors"). A vendor identification string is returned in the EBX, EDX, and ECX registers. For Intel(R) processors, the vendor identification string is GenuineIntel as follows:

EBX ←756e6547h (* "Genu", with G in the low nibble of BL *)

EDX ←49656e69h (* "ineI", with i in the low nibble of DL *)

ECX ←6c65746eh (* "ntel", with n in the low nibble of CL *)

When the input value is 1, the processor returns version information in the EAX register (see "Version Information in the EAX Register"). The version information consists of an IA-32 processor family identifier, a model identifier, a stepping ID, and a processor type. The model, family, and processor type for the first processor in the Intel Pentium 4 processor family is as follows:

• Model0000B

• Family1111B

• Processor Type00B

The available processor types are given in the table "Processor Type Field". Intel releases information on stepping IDs as needed.

Version Information in the EAX Register

Processor Type Field

Note

* Not applicable to Intel486 processors.

If the values in the family and/or model fields reach or exceed FH, the CPUID instruction will generate two additional fields in the EAX register: the extended family field and the extended model field. Here, a value of FH in either the model field or the family field indicates that the extended model or family field, respectively, is valid. Family and model numbers beyond FH range from 0FH to FFH, with the least significant hexadecimal digit always FH.

See AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) and Chapter 13 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for more information on identifying earlier IA-32 processors.

When the input value in EAX is 1, three unrelated pieces of information are returned to the EBX register:

• Brand index (low byte of EBX)this number provides an entry into a brand string table that contains brand strings for IA-32 processors. See Brand Identification later in the description of this instruction for information about the intended use of brand indices. This field was introduced in the Pentium(R) III Xeon(R) processors.

• CLFLUSH instruction cache line size (second byte of EBX)this number indicates the size of the cache line flushed with CLFLUSH instruction in 8-byte increments. This field was introduced in the Pentium 4 processor.

• Local APIC ID (high byte of EBX)this number is the 8-bit ID that is assigned to the local APIC on the processor during power up. This field was introduced in the Pentium 4 processor.

When the input value in EAX is 1, feature information is returned to the EDX register (see "Feature Information in the EDX Register"). The feature bits permit operating system or application code to determine which IA-32 architectural features are available in the processor. The table "CPUID Feature Flags Returned in EDX Register" shows the encoding of the feature flags in the EDX register. For all the feature flags currently returned in EDX, a 1 indicates that the corresponding feature is supported. Software should identify Intel as the vendor to properly interpret the feature flags. Software should not depend on a 1 indicating the presence of a feature for future feature flags.

Feature Information in the EDX Register

CPUID Feature Flags Returned in EDX Register

If a higher value than is shown in "Information Returned by CPUID Instruction" is entered for a particular processor, the information for the highest useful basic information value is returned. For example, if an input value of 5 is entered in EAX for a Pentium 4 processor, the information for an input value of 2 is returned. The exception to this rule is the input values that return extended function information (currently, the values 80000000H through 80000004H). For a Pentium 4 processor, entering an input value of 80000005H or above, returns the information for an input value of 2.

The CPUID instruction can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed (see Serializing Instructions in Chapter 7 of the IA-32 Intel(R) Architecture Software Developer's Manual, Volume 3).

When the input value in the EAX register is 0, the processor returns the highest value the CPUID instruction recognizes in the EAX register for returning basic CPUID information (see the table "Highest CPUID Source Operand for IA-32 Processors"). A vendor identification string is returned in the EBX, EDX, and ECX registers. For Intel(R) processors, the vendor identification string is GenuineIntel as follows:

EBX ←756e6547h (* "Genu", with G in the low nibble of BL *)

EDX ←49656e69h (* "ineI", with i in the low nibble of DL *)

ECX ←6c65746eh (* "ntel", with n in the low nibble of CL *)

When the input value is 1, the processor returns version information in the EAX register (see "Version Information in the EAX Register"). The version information consists of an IA-32 processor family identifier, a model identifier, a stepping ID, and a processor type. The model, family, and processor type for the first processor in the Intel Pentium 4 processor family is as follows:

• Model0000B

• Family1111B

• Processor Type00B

The available processor types are given in the table "Processor Type Field". Intel releases information on stepping IDs as needed.

Version Information in the EAX Register

Processor Type Field

Note

* Not applicable to Intel486 processors.

If the values in the family and/or model fields reach or exceed FH, the CPUID instruction will generate two additional fields in the EAX register: the extended family field and the extended model field. Here, a value of FH in either the model field or the family field indicates that the extended model or family field, respectively, is valid. Family and model numbers beyond FH range from 0FH to FFH, with the least significant hexadecimal digit always FH.

See AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) and Chapter 13 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for more information on identifying earlier IA-32 processors.

When the input value in EAX is 1, three unrelated pieces of information are returned to the EBX register:

• Brand index (low byte of EBX) this number provides an entry into a brand string table that contains brand strings for IA-32 processors. See Brand Identification later in the description of this instruction for information about the intended use of brand indices. This field was introduced in the Pentium(R) III Xeon(R) processors.

• CLFLUSH instruction cache line size (second byte of EBX) this number indicates the size of the cache line flushed with CLFLUSH instruction in 8-byte increments. This field was introduced in the Pentium 4 processor.

• Local APIC ID (high byte of EBX) this number is the 8-bit ID that is assigned to the local APIC on the processor during power up. This field was introduced in the Pentium 4 processor.

When the input value in EAX is 1, feature information is returned to the EDX register (see "Feature Information in the EDX Register"). The feature bits permit operating system or application code to determine which IA-32 architectural features are available in the processor. The table "CPUID Feature Flags Returned in EDX Register" shows the encoding of the feature flags in the EDX register. For all the feature flags currently returned in EDX, a 1 indicates that the corresponding feature is supported. Software should identify Intel as the vendor to properly interpret the feature flags. Software should not depend on a 1 indicating the presence of a feature for future feature flags.

Feature Information in the EDX Register

CPUID Feature Flags Returned in EDX Register

When the input value is 2, the processor returns information about the processor's internal caches and TLBs in the EAX, EBX, ECX, and EDX registers. The encoding of these registers is as follows:

• The least-significant byte in register EAX (register AL) indicates the number of times the CPUID instruction must be executed with an input value of 2 to get a complete description of the processor's caches and TLBs. The first member of the family of Pentium 4 processors will return a 1.

• The most significant bit (bit 31) of each register indicates whether the register contains valid information (set to 0) or is reserved (set to 1).

• If a register contains valid information, the information is contained in 1 byte descriptors. The table "Encoding of Cache and TLB Descriptors" shows the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache or TLB types. The descriptors may appear in any order.

Encoding of Cache and TLB Descriptors

The first member of the family of Pentium 4 processors will return the following information about caches and TLBs when the CPUID instruction is executed with an input value of 2:

EAX 66 5B 50 01H

EBX 0H

ECX 0H

EDX 00 7A 70 00H

These values are interpreted as follows:

• The least-significant byte (byte 0) of register EAX is set to 01H, indicating that the CPUID instruction needs to be executed only once with an input value of 2 to retrieve complete information about the processor's caches and TLBs.

• The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register contains valid 1-byte descriptors.

• Bytes 1, 2, and 3 of register EAX indicate that the processor contains the following:

•  50HA 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages.

• 5BHA 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.

• 66HAn 8-KByte 1st level data cache, 4-way set associative, with a 64-byte cache line size.

• The descriptors in registers EBX and ECX are valid, but contain null descriptors.

• Bytes 0, 1, 2, and 3 of register EDX indicate that the processor contains the following:

• 00HNull descriptor.

• 70HA 12-KByte 1st level code cache, 4-way set associative, with a 64-byte cache line size.

• 7AHA 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size.

• 00HNull descriptor.

Brand Identification

To facilitate brand identification of IA-32 processors with the CPUID instruction, two features are provided: brand index and brand string.

The brand index was added to the CPUID instruction with the Pentium III Xeon processor and will be included on future IA-32 processors, including the Pentium 4 processors. The brand index provides an entry point into a brand identification table that is maintained in memory by system software and is accessible from system- and user-level code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official Intel family and model number of a processor (for example, Intel Pentium III processor).

When executed with a value of 1 in the EAX register, the CPUID instruction returns the brand index to the low byte in EBX. Software can then use this index to locate the brand identification string for the processor in the brand identification table. The first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not support the brand identification feature. The table "Mapping of Brand Indices and IA-32 Processor Brand Strings" shows those brand indices that currently have processor

brand identification strings associated with them.

It is recommended that

1. All reserved entries included in the brand identification table be associated with a brand string that indicates that the index is reserved for future Intel processors.

2. Software be prepared to handle reserved brand indices gracefully.

Mapping of Brand Indices and IA-32 Processor Brand Strings

Indicates versions of these processors that were introduced after the Pentium III Xeon processor.

The brand string feature is an extension to the CPUID instruction introduced in the Pentium 4 processors. With this feature, the CPUID instruction returns the ASCII brand identification string and the maximum operating frequency of the processor to the EAX, EBX, ECX, and EDX registers. (Note that the frequency returned is the maximum operating frequency that the

processor has been qualified for and not the current operating frequency of the processor.)

To use the brand string feature, the CPUID instructions must be executed three times, once with an input value of 8000002H in the EAX register, and a second time an input value of 80000003, and a third time with a value of 80000004H.

The brand string is architecturally defined to be 48 byte long: the first 47 bytes contain ASCII characters and the 48th byte is defined to be null (0). The string may be right justified (with leading spaces) for implementation simplicity. For each input value (EAX is 80000002H, 80000003H, or 80000004H), the CPUID instruction returns 16 bytes of the brand string to the EAX, EBX, ECX, and EDX registers. Processor implementations may return less than the 47 ASCII characters, in which case the string will be null terminated and the processor will return valid data for each of the CPUID input values of 80000002H, 80000003H, and 80000004H.

Table "Processor Brand String Returned with First Pentium 4 Processor" shows the brand string that is returned by the first processor in the family of Pentium 4 processors.

Note

When a frequency is given in a brand string, it is the maximum qualified frequency of the processor, not the actual frequency the processor is running at.

The following procedure can be used for detection of the brand string feature:

1. Execute the CPUID instruction with input value in EAX of 80000000H.

2. If ((EAX_Return_Value) AND (80000000H) ≠0) then the processor supports the extended CPUID functions and EAX contains the largest extended function input value supported.

3. If EAX_Return_Value ≥80000004H, then the CPUID instruction supports the brand string feature.

Processor Brand String Returned with First Pentium(R) 4 Processor

To identify an IA-32 processor using the CPUID instruction, brand identification software

should use the following brand identification techniques ordered by decreasing priority:

• Processor brand string

• Processor brand index and a software supplied brand string table.

• Table based mechanism using type, family, model, stepping, and cache information returned by the CPUID instruction.

IA-32 Architecture Compatibility.

The CPUID instruction is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the Intel486 processor.

Operation

CASE (EAX) OF

EAX =0:

EAX ←highest basic function input value understood by CPUID;

EBX ←Vendor identification string;

EDX ←Vendor identification string;

ECX ←Vendor identification string;

BREAK;

EAX =1H:

EAX[3:0] ←Stepping ID;

EAX[7:4] ←Model;

EAX[11:8] ←Family;

EAX[13:12] ←Processor type;

EAX[15:14] ←Reserved;

EAX[19:16] ←Extended Model;

EAX[23:20] ←Extended Family;

EAX[31:24] ←Reserved;

EBX[7:0] ←Brand Index;

EBX[15:8] ←CLFLUSH Line Size;

EBX[16:23] ←Reserved;

EBX[24:31] ←Initial APIC ID;

ECX ←Reserved;

EDX ←Feature flags; (* See Figure 3-4 *)

BREAK;

EAX =2H:

EAX ←Cache and TLB information;

EBX ←Cache and TLB information;

ECX ←Cache and TLB information;

EDX ←Cache and TLB information;

BREAK;

EAX =3H:

EAX ←Reserved;

EBX ←Reserved;

ECX ←ProcessorSerialNumber[31:0];

(* Pentium III processors only, otherwise reserved *)

EDX ←ProcessorSerialNumber[63:32];

(* Pentium III processors only, otherwise reserved *

BREAK;

EAX =80000000H:

EAX ←highest extended function input value understood by CPUID;

EBX ←Reserved;

ECX ←Reserved;

EDX ←Reserved;

BREAK;

EAX =80000001H:

EAX ←Extended Processor Signature and Feature Bits (*Currently Reserved*);

EBX ←Reserved;

ECX ←Reserved;

EDX ←Reserved;

BREAK;

EAX =80000002H:

EAX ←Processor Name;

EBX ←Processor Name;

ECX ←Processor Name;

EDX ←Processor Name;

BREAK;

EAX =80000003H:

EAX ←Processor Name;

EBX ←Processor Name;

ECX ←Processor Name;

EDX ←Processor Name;

BREAK;

EAX =80000004H:

EAX ←Processor Name;

EBX ←Processor Name;

ECX ←Processor Name;

EDX ←Processor Name;

BREAK;

DEFAULT: (* EAX >highest value recognized by CPUID *)

EAX ←Reserved; (* undefined*)

EBX ←Reserved; (* undefined*)

ECX ←Reserved; (* undefined*)

EDX ←Reserved; (* undefined*)

BREAK;

ESAC;

Flags Affected

None.

Exceptions (All Operating Modes)

None.

Note

In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated.

For details, see Volume 2A and Volume 2B of the 1.11 Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.