SGDT/SIDT--Store Global/Interrupt Descriptor Table Register

Description

Stores the contents of the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR) in the destination operand. The destination operand specifies a 6-byte memory location. If the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the lower 2 bytes of the memory location and the 32-bit base address is stored in the upper 4 bytes. If the operand-size attribute is 16 bits, the limit is stored in the lower 2 bytes and the 24-bit base address is stored in the third, fourth, and fifth byte, with the sixth byte filled with 0s.

The SGDT and SIDT instructions are only useful in operating-system software; however, they can be used in application programs without causing an exception to be generated.

See LGDT/LIDT--Load Global/Interrupt Descriptor Table Register in this chapter for information on loading the GDTR and IDTR.

Intel(R) Architecture Compatibility

The 16-bit forms of the SGDT and SIDT instructions are compatible with the Intel(R) 286 processor, if the upper 8 bits are not referenced. The Intel(R) 286 processor fills these bits with 1s; the Pentium(R) Pro, Pentium, Intel486™, and Intel386™ processors fill these bits with 0s.

Operation

IF instruction is IDTR
THEN
IF OperandSize 16
THEN
DEST[0:15] IDTR(Limit);
DEST[16:39] IDTR(Base); (* 24 bits of base address loaded; *)
DEST[40:47] 0;
ELSE (* 32-bit Operand Size *)
DEST[0:15] IDTR(Limit);
DEST[16:47] IDTR(Base); (* full 32-bit base address loaded *)
FI;
ELSE (* instruction is SGDT *)
IF OperandSize 16
THEN
DEST[0:15] GDTR(Limit);
DEST[16:39] GDTR(Base); (* 24 bits of base address loaded; *)
DEST[40:47] 0;
ELSE (* 32-bit Operand Size *)
DEST[0:15] GDTR(Limit);
DEST[16:47] GDTR(Base); (* full 32-bit base address loaded *)
FI; FI;

Flags Affected

None.

Protected Mode Exceptions

#UD - If the destination operand is a register.

#GP(0) - If the destination is located in a nonwritable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#PF(fault-code) - If a page fault occurs.

#AC(0) - If an unaligned memory access occurs when the CPL is 3 and alignment checking is enabled.

Real-Address Mode Exceptions

#UD - If the destination operand is a register.

#GP - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS - If a memory operand effective address is outside the SS segment limit.

Virtual-8086 Mode Exceptions

#UD - If the destination operand is a register.

#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#PF(fault-code) - If a page fault occurs.

#AC(0) - If an unaligned memory access occurs when alignment checking is enabled.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.