LGDT/LIDT--Load Global/Interrupt Descriptor Table Register

Description

Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a linear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32-bit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute is 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here, the high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is filled with zeros.

The LGDT and LIDT instructions are used only in operating-system software; they are not used in application programs. They are the only instructions that directly load a linear address (that is, not a segment-relative address) and a limit in protected mode. They are commonly executed in real-address mode to allow processor initialization prior to switching to protected mode.

See SFENCE--Store Fence in this chapter for information on storing the contents of the GDTR and IDTR.

Operation

IF instruction is LIDT
THEN
IF OperandSize 16
THEN
IDTR(Limit) SRC[0:15];
IDTR(Base) SRC[16:47] AND 00FFFFFFH;
ELSE (* 32-bit Operand Size *)
IDTR(Limit) SRC[0:15];
IDTR(Base) SRC[16:47];
FI;
ELSE (* instruction is LGDT *)
IF OperandSize 16
THEN
GDTR(Limit) SRC[0:15];
GDTR(Base) SRC[16:47] AND 00FFFFFFH;
ELSE (* 32-bit Operand Size *)
GDTR(Limit) SRC[0:15];
GDTR(Base) SRC[16:47];
FI; FI;

Flags Affected

None.

Protected Mode Exceptions

#UD - If source operand is not a memory location.

#GP(0) - If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#PF(fault-code) - If a page fault occurs.

Real-Address Mode Exceptions

#UD - If source operand is not a memory location.

#GP - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS - If a memory operand effective address is outside the SS segment limit.

Virtual-8086 Mode Exceptions

#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.