Guideline for MONITOR/MWAIT

MONITOR and MWAIT are provided to improve synchronization between multiple agents. In the implementation for the Intel® Pentium®4 processor with Streaming SIMD Extensions 3 (SSE3), MONITOR/MWAIT are targeted for use by system software to provide more efficient thread synchronization primitives. MONITOR defines an address range used to monitor write-back stores. MWAIT is used to indicate that the software thread is waiting for a write-back store to the address range defined by the MONITOR instruction.

MONITOR/MWAIT Address Range Determination

Software should know the exact length of the region that will be monitored for writes by the MONITOR/MWAIT. Allocating and using a region smaller in length than the triggering area for the processor could lead to false wake-ups (resulting from writes to data variables that are incorrectly located in the triggering area). Conversely, allocating a region greater in length than the triggering area could lead to the processor not waking appropriately. CPUID allows for the determination of the exact length of the triggering area. This length has no relationship to any cache line size in the system and software should not make any assumptions to that effect. Based on the size provided by CPUID, the OS/software should dynamically allocate structures with appropriate padding. If correct allocation causes issues, choose to not use MONTIOR/MWAIT.

While a single length is expected to suffice for single cluster based systems, setting up the data layout for systems with multiple clusters is expected to be more complicated. Depending on the mechanism implemented by the chipset in such a system, a single monitor-line size may not suffice.

Typically software will have a set of data variables that it monitors for writes. It will be necessary to locate these in the monitor triggering area. To eliminate false wake-ups due to writes to other variables, software will need to add padding around the monitored variables. This is referred to as the padded area.

Waking-up From MWAIT

Multiple events other than a write to the triggering address range can cause a processor that executed MWAIT to wake up. These include:

External interrupts: NMI, SMI, INIT, BINIT, MCERR
Faults, Aborts including Machine Check
Architectural TLB invalidations, including writes to CR0, CR3, CR4 and certain MSR writes
Voluntary transitions due to fast system call and far calls

Power management related events such as Thermal Monitor or chipset driven STP-CLK# assertions will not cause the Monitor event pending bit to be cleared. Debug traps and faults will not cause the Monitor event pending bit to be cleared.

The following example shows the typical usage of MONITOR/MWAIT.

Pseudo Code to Use MONITOR/MWAIT

// Trigger[MONITORDATARANGE] is the memory address range that will be

// used as the trigger data range Trigger[0] = 0;

If ( trigger[0] != TRIGERRDATAVALUE) {

EAX = &trigger[0]

ECX = 0

EDX = 0

MONITOR EAX, ECX, EDX

If (trigger[0] != TRIGERRDATAVALUE ) {

EAX = 0

ECX = 0

MWAIT EAX, ECX

}

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.