Edit Events Dialog Box for Systems with Intel(R) Itanium(R) Processors

ISM

Bit 25:24. Instruction Set Mask (ISM). Controls performance monitor operation based on the current instruction set.

The instruction set mask applies to PMC[4, 5, 6, 7, 10, 11] but not to PMC[12].

00: monitoring enabled during Itanium(R) processor and IA-32 architecture instruction execution (regardless of PSR.is)

10:bit 24 low enables monitoring during Itanium processor instruction execution (when PSR.is is zero)

01:bit 25 low enables monitoring during IA-32 architecture instruction execution (when PSR.is is one)

11: disables monitoring

Threshold

Bit 22:20. Threshold - enables thresholding for "multi-occurrence" events.

PMC[4,5] define 3 threshold bits 22:20, while PMC[6,7] define 2 threshold bits 21:20.

When threshold is zero, the counter sums up all observed event values. When the threshold is non-zero, the counter increments by one in every cycle in which the observed event value exceeds the threshold.

UMASK

Bit 19:16. Unit mask - event specific mask bits.

if tlb=0: Instruction cache unit mask

if tlb=1: Instruction TLB unit mask

ES

Event select, bit 14:8. Selects the performance event to be monitored.

PLM

Bit 3:0. Privilege Level Mask (PLM). Controls performance monitor operation for a specific privilege level. Each bit corresponds to one of the 4 privilege levels, with bit 0 corresponding to privilege level 0, bit 1 with privilege level 1, etc. A bit value of 1 indicates that the monitor is enabled at that privilege level. Writing zeroes to all plm bits effectively disables the monitor. In this state, the Itanium processor will not preserve the value of the corresponding PMD register(s).

External Visibility (ev)

Bit 4. When 1, an external notification (BPM pin strobe) is provided whenever the counter wraps, i.e. a carry out from bit 31 is detected. External notification occurs regardless of the setting of the oi bit. On the Itanium processor, PMC[4] external notification strobes the BPM0 pin, PMC[5] external notification strobes the BPM1 pin, PMC[6] external notification strobes the BPM2 pin, and PMC[7] external notification strobes the BPM3 pin.

Overflow Interrupt (oi)

Bit 5. When 1, a Performance Monitor interrupt is raised and the performance monitor freeze bit (PMC[0].fr) is set when the monitor overflows. When 0, no interrupt is raised and the performance monitor freeze bit (PMC[0].fr) remains unchanged. Overflow occurs when the counter wraps, i.e. a carry out from bit 31 is detected. Counter overflow generate only one interrupt.

Privilege Monitor (pm)

When 0, the performance monitor is configured as a user monitor, and enabled by PSR.up. When PMC.pm is 1, the performance monitor is configured as a privileged monitor, enabled by PSR.pp, and PMD can only be read by privileged software.

When PMC[10].tlb is one, the instruction event address register captures addresses of instruction TLB misses. The unit mask allows event address collection to capture specific subsets of instruction TLB misses.

When PMC[10].tlb is zero, the instruction event address register captures instruction addresses and access latencies for L1 instruction cache misses. Only misses whose latency exceeds a programmable threshold are captured. The threshold is specified as a four bit umask field in the configuration register PMC[10].

Enable Calibration

Enabling calibration adjusts the sampling frequency (the Sample After value) to collect the target number of samples over the entire duration of the Activity.

If calibration is not enabled, there will be no  calibration run prior to collecting data and the default sample after value will be used to collect data.

To calibrate all events selected for event-based sampling (even when the Enable Calibration is unchecked for certain events), choose the Calibrate Sample After Value for all the selected events option in the General tab when configuring an Activity with the sampling collector.