L1 D-Cache Miss per InstructionL1 D-Cache Miss per InstructionL1 Data Lines Allocated / Instructions Retired
This ratio calculates the number of L1 data cache misses per instructions retired resulting from load or store operations. A high value of this ratio indicates high penalty for load and store operations that do not have data in the L1 cache.
Limits: good < 0.02, bad > 0.08
Tip Handle the L2 Miss per Instruction Ratio first, until it is low
Improve data locality
Use data buffers that fit in the L1 data cache
If the examined code contains long repeat instructions this ratio may show a value that is high but yet does not represent a performance issue. To detect whether there are long repeat instructions you can use the uOps per Instructions Retired ratio.