Prefix Penalty Indicator

Prefix_Pen indicates a penalty condition.

The instruction for which Prefix_Pen is issued has a prefix. Prefixed instructions increase fetch time.

Instructions with lock, segment-override, address-size override, and operand-size override prefixes cause a prefix penalty on Pentium(R) processors and on Pentium processors with MMX technology. This means that all 16-bit instructions executing in 32-bit mode also result in a prefix penalty.

On Pentium processors, a prefixed instruction takes one additional cycle.

On Pentium processors with MMX(TM) technology, if the prefix is ready in the FIFO buffer, there is no prefix penalty. Otherwise, operand-size override prefixes may cause a zero to three-cycle stall. All other prefixes may cause a one-cycle stall.

The presence of the two-byte opcode map (0F) in the instruction field does not cause a penalty.

On Pentium processors with MMX technology, in the static-analysis view, the VTune(TM) Performance Analyzer assumes that, at the start of every basic block, there is no prefix penalty (because the instructions are ready in the FIFO buffer).

Advice

Try to avoid using prefixed instructions. Follow these guidelines:

• Do not reference word data types in 32-bit mode, or long data types in 16-bit mode.

• Do not use segment registers instead of general registers.

• Use the DS segment register to access the data segment when possible. Instructions with other segment registers have a one-byte, segment-override prefix.

• Place prefixed instructions after a multi-cycle instruction to prevent the prefix penalty.

Example:

1. mov ax, WORD PTR mem
2. and ax, bx
3. and ax, 0xfff

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1. mov eax, DWORD PTR mem
2. and eax, 0xfff
3. and eax, ebx

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