of the appropriate sign is stored in the destination
operand.
Opcode |
Instruction |
Description |
|---|---|---|
|
D8 /7 |
FDIVR m32real |
Divide m32real by ST(0) and store result in ST(0) |
|
DC /7 |
FDIVR m64real |
Divide m64real by ST(0) and store result in ST(0) |
|
D8 F8+i |
FDIVR ST(0), ST(i) |
Divide ST(i) by ST(0) and store result in ST(0) |
|
DC F0+i |
FDIVR ST(i), ST(0) |
Divide ST(0) by ST(i) and store result in ST(i) |
|
DE F0+i |
FDIVRP ST(i), ST(0) |
Divide ST(0) by ST(i), store result in ST(i), and pop the register stack |
|
DE F1 |
FDIVRP |
Divide ST(0) by ST(1), store result in ST(1), and pop the register stack |
|
DA /7 |
FIDIVR m32int |
Divide m32int by ST(0) and store result in ST(0) |
|
DE /7 |
FIDIVR m16int |
Divide m16int by ST(0) and store result in ST(0) |
Divides the source operand by the destination operand and stores the result in the destination location. The destination operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory location. Source operands in memory can be in single-real, double-real, word-integer, or short-integer formats.
These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to support more efficient coding.
The no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1) register. The one-operand version divides the contents of a memory location (either a real or an integer value) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by the contents of the ST(0) register or vice versa.
The FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point divide instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FDIVR rather than FDIVRP.
The FIDIVR instructions convert an integer source operand to extended-real format before performing the division.
If an unmasked divide-by-zero exception (#Z) is generated, no result
is stored; if the exception is masked, an of the appropriate sign is stored in the destination
operand.
The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs.
|
|
DEST |
|
|
|
|
|
|
| |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SRC |
|
- |
-F |
-0 |
+0 |
+F |
+ |
NaN |
|
|
|
|
|
|
|
|
|
- |
* |
+ |
+ |
- |
- |
* |
NaN |
|
|
|
|
|
| |
|
|
-F |
+0 |
+F |
** |
** |
-F |
-0 |
NaN |
|
|
|
|
|
| |
|
|
-I |
+0 |
+F |
** |
** |
-F |
-0 |
NaN |
|
|
|
|
|
| |
|
|
-0 |
+0 |
+0 |
* |
* |
-0 |
-0 |
NaN |
|
|
|
|
|
| |
|
|
+0 |
-0 |
-0 |
* |
* |
+0 |
+0 |
NaN |
|
|
|
|
|
| |
|
|
+I |
-0 |
-F |
** |
** |
+F |
+0 |
NaN |
|
|
|
|
|
| |
|
|
+F |
-0 |
-F |
** |
** |
+F |
+0 |
NaN |
|
|
|
|
|
| |
|
|
+ |
* |
- |
- |
+ |
+ |
* |
NaN |
|
|
|
|
|
| |
|
|
NaN |
NaN |
NaN |
NaN |
NaN |
NaN |
NaN |
NaN |
|
|
|
|
|
| |
Note F Means finite-real number.
I Means integer.
* Indicates floating-point invalid-arithmetic-operand (#IA) exception.
** Indicates floating-point zero-divide (#Z) exception.
When the source operand is an integer 0, it is treated as a +0.
IF DEST = 0
THEN
#Z
ELSE
IF instruction is FIDIVR
THEN
DEST 
ConvertExtendedReal(SRC)
/ DEST;
ELSE (* source operand is real number *)
DEST SRC / DEST;
FI;
FI;
IF instruction FDIVRP
THEN
PopRegisterStack
FI;
C1 - Set to 0 if stack underflow occurred. Indicates rounding direction if the inexact-result exception (#P) is generated:
0 not roundup;
1 roundup.
C0, C2, C3 - Undefined.
#IS Stack underflow occurred.
#IA Operand is an SNaN value or unsupported format.
±∞ / ±∞; ±0 / ±0
#D Source is a denormal value.
#Z SRC / ±0, where SRC is not equal to ±0.
#U Result is too small for destination format.
#O Result is too large for destination format.
#P Value cannot be represented exactly in destination format.
#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a null segment selector.
#SS(0) - If a memory operand effective address is outside the SS segment limit.
#NM - EM or TS in CR0 is set.
#PF(fault-code) - If a page fault occurs.
#AC(0) - If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#GP - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS - If a memory operand effective address is outside the SS segment limit.
#NM - EM or TS in CR0 is set.
#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0) - If a memory operand effective address is outside the SS segment limit.
#NM - EM or TS in CR0 is set.
#PF(fault-code) - If a page fault occurs.
#AC(0) - If alignment checking is enabled and an unaligned memory reference is made.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.