+0.0.
Opcode |
Instruction |
Description |
|---|---|---|
|
DB F0+i |
FCOMI ST, ST(i) |
Compare ST(0) with ST(i) and set status flags accordingly |
|
DF F0+i |
FCOMIP ST, ST(i) |
Compare ST(0) with ST(i), set status flags accordingly, and pop register stack |
|
DB E8+i |
FUCOMI ST, ST(i) |
Compare ST(0) with ST(i), check for ordered values, and set status flags accordingly |
|
DF E8+i |
FUCOMIP ST, ST(i) |
Compare ST(0) with ST(i), check for ordered values, set status flags accordingly, and pop register stack |
Compares the contents of register ST(0) and ST(i) and sets the status
flags ZF, PF, and CF in the EFLAGS register according to the results (see
the table below). The sign of zero is ignored for comparisons, so that
-0.0 +0.0.
Comparison Results |
ZF |
PF |
CF |
|---|---|---|---|
|
ST0 > ST(i) |
0 |
0 |
0 |
|
ST0 < ST(i) |
0 |
0 |
1 |
|
ST0
|
1 |
0 |
0 |
|
Unordered* |
1 |
1 |
1 |
Note * Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.
The FCOMI/FCOMIP instructions perform the same operation as the FUCOMI/FUCOMIP instructions. The only difference is how they handle QNaN operands. The FCOMI/FCOMIP instructions set the status flags to "unordered" and generate an invalid-arithmetic-operand exception (#IA) when either or both of the operands is a NaN value (SNaN or QNaN) or is in an unsupported format.
The FUCOMI/FUCOMIP instructions perform the same operation as the FCOMI/FCOMIP instructions, except that they do not generate an invalid-arithmetic-operand exception for QNaNs. See FXAM--Examine in this chapter for additional information on unordered comparisons.
If invalid-operation exception is unmasked, the status flags are not set if the invalid-arithmetic-operand exception is generated.
The FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions clear the OF flag in the EFLAGS register (regardless of whether an invalid-operation exception is detected).
The FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were introduced to the Intel(R) Architecture in the Pentium(R) Pro processor family and are not available in earlier Intel(R) Architecture processors.
CASE (relation of operands) OF
ST(0) > ST(i): ZF, PF, CF 000;
ST(0) < ST(i): ZF, PF, CF 001;
ST(0) ST(i): ZF,
PF, CF 100;
ESAC;
IF instruction is FCOMI or FCOMIP
THEN
IF ST(0) or ST(i)
NaN or unsupported format
THEN
#IA
IF FPUControlWord.IM
1
THEN
ZF, PF, CF 111;
FI;
FI;
FI;
IF instruction is FUCOMI or FUCOMIP
THEN
IF ST(0) or ST(i)
QNaN, but not SNaN or unsupported format
THEN
ZF, PF, CF 111;
ELSE (* ST(0) or ST(i) is SNaN or unsupported format *)
#IA;
IF FPUControlWord.IM
1
THEN
ZF, PF, CF 111;
FI;
FI;
FI;
IF instruction is FCOMIP or FUCOMIP
THEN
PopRegisterStack;
FI;
C1 - Set to 0 if stack underflow occurred; otherwise, cleared to 0.
C0, C2, C3 - Not affected.
#IS - Stack underflow occurred.
#IA (FCOMI or FCOMIP instruction) - One or both operands are NaN values or have unsupported formats. (FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or have undefined formats. Detection of a QNaN value does not raise an invalid-operand exception.
#NM - EM or TS in CR0 is set.
#NM - EM or TS in CR0 is set.
#NM - EM or TS in CR0 is set.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.