DEST[63-0] / SRC[63-0];* DEST[127-64] remains unchanged *;
Opcode |
Instruction |
Description |
|---|---|---|
|
F2 0F 5E /r |
DIVSD xmm1, xmm2/m64 |
Divide low double-precision floating-point value n xmm1 by low double-precision floating-point value in xmm2/mem64. |
Divides the low double-precision floating-point value in the destination operand (first operand) by the low double-precision floating-point value in the source operand (second operand), and stores the double-precision floating-point result in the destination operand. The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. The high quadword of the destination operand remains unchanged. See Figure 11-4 in the IA-32 Intel(R) Architecture Software Developer's Manual, Volume 1 for an illustration of a scalar double-precision floating-point operation.
DEST[63-0] DEST[63-0] / SRC[63-0];
* DEST[127-64] remains unchanged *;
DIVSD __m128d _mm_div_sd (m128d a, m128d b)
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.
#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0) - For an illegal address in the SS segment.
#PF(fault-code) - For a page fault.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
#AC - For unaligned memory reference if the current privilege level is 3.
Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.
Same exceptions as in Real Address Mode.
#PF(fault-code) - For a page fault.
#AC - For unaligned memory reference if the current privilege level is 3.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.