CVTPD2DQ--Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers

Converts two packed double-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The result is stored in the low quadword of the destination operand and the high quadword is cleared to all 0s.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.

Operation

DEST[31-0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63-0]);
DEST[63-32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127-64]);
DEST[127-64] 0000000000000000H;

Intel(R) C++ Compiler Intrinsic Equivalent

CVTPD2DQ __m128d _mm_cvtpd_epi32(__m128d a)

SIMD Floating-Point Exceptions

Invalid, Precision.

Protected Mode Exceptions

#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If memory operand is not aligned on a 16-byte boundary, regardless of segment.

#SS(0) - For an illegal address in the SS segment.

#PF(fault-code) - For a page fault.

#NM - If TS in CR0 is set.

#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

Real-Address Mode Exceptions

#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment.

Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.

#NM - If TS in CR0 is set.

#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#PF(fault-code) - For a page fault.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.