XADD--Exchange and Add

Description

Exchanges the first operand (destination operand) with the second operand (source operand), then loads the sum of the two values into the destination operand. The destination operand can be a register or a memory location; the source operand is a register.

This instruction can be used with a LOCK prefix.

Intel(R) Architecture Compatibility

Intel(R) Architecture processors earlier than the Intel486™ processor do not recognize this instruction. If this instruction is used, you should provide an equivalent code sequence that runs on earlier processors.

Operation

TEMP SRC + DEST
SRC DEST
DEST TEMP

Flags Affected

The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination operand.

Protected Mode Exceptions

#GP(0) - If the destination is located in a nonwritable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a null segment selector.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#PF(fault-code) If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

#GP - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS - If a memory operand effective address is outside the SS segment limit.

Virtual-8086 Mode Exceptions

#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#PF(fault-code) - If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.