DEST[31-0] - SRC[31-0];* DEST[127-96] remains unchanged *;
Opcode |
Instruction |
Description |
|---|---|---|
|
F3 0F 5C /r |
SUBSS xmm1, xmm2/m32 |
Subtract the lower single-precision floating-point numbers in xmm2/m32 from xmm1. |
Subtracts the low single-precision floating-point value in the source operand (second operand) from the low single-precision floating-point value in the destination operand (first operand), and stores the single-precision floating-point result in the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the IA-32 Intel(R) Architecture Software Developer's Manual, Volume 1 for an illustration of a scalar single-precision floating-point operation.
DEST[31-0] DEST[31-0] - SRC[31-0];
* DEST[127-96] remains unchanged *;
SUBSS __m128 _mm_sub_ss(__m128 a, __m128 b)
Overflow, Underflow, Invalid, Precision, Denormal.
#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0) - For an illegal address in the SS segment.
#PF(fault-code) - For a page fault.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
#AC - For unaligned memory reference if the current privilege level is 3.
Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
Same exceptions as in Real Address Mode.
#PF(fault-code) - For a page fault.
#AC - For unaligned memory reference if the current privilege level is 3.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.