Opcode |
Instruction |
Description |
---|---|---|
FB |
STI |
Set interrupt flag; external, maskable interrupts enabled at the end of the next instruction |
Sets the interrupt flag (IF) in the EFLAGS register. After the IF flag is set, the processor begins responding to external, maskable interrupts after the next instruction is executed. The delayed effect of this instruction is provided to allow interrupts to be enabled just before returning from a procedure (or subroutine). For instance, if an STI instruction is followed by an RET instruction, the RET instruction is allowed to execute before external interrupts are recognized. This behavior allows external interrupts to be disabled at the beginning of a procedure and enabled again at the end of the procedure. If the STI instruction is followed by a CLI instruction (which clears the IF flag), the effect of the STI instruction is negated.
The IF flag and the STI and CLI instructions have no affect on the generation of exceptions and NMI interrupts.
The following decision table indicates the action of the STI instruction (bottom of the table) depending on the processor's mode of operation and the CPL and IOPL of the currently running program or procedure (top of the table).
PE = |
0 |
1 |
1 |
1 |
VM = |
X |
0 |
0 |
1 |
CPL |
X |
IOPL |
> IOPL |
=3 |
IOPL |
X |
X |
X |
=3 |
IF 1 |
Y |
Y |
N |
Y |
#GP(0) |
N |
N |
Y |
N |
"X" means Don't care
"N" means Action in Column 1 not taken
"Y" means Action in Column 1 taken
IF PE=0 (* Executing in real-address mode *)
THEN
IF 1; (* Set Interrupt
Flag *)
ELSE (* Executing in protected mode or virtual-8086 mode *)
IF VM=0 (* Executing in protected mode*)
THEN
IF IOPL 3
THEN
IF 1;
ELSE
IF CPL IOPL
THEN
IF 1;
ELSE
#GP(0);
FI;
FI;
ELSE (* Executing in Virtual-8086 mode *)
#GP(0); (* Trap to virtual-8086 monitor *)
FI;
FI;
The IF flag is set to 1.
#GP(0) - If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
None.
#GP(0) - If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.