Opcode |
Instruction |
Description |
|---|---|---|
|
0F C6 /r ib |
SHUFPS xmm1, xmm2/m128, imm8 |
Shuffle packed single-precision floating-point values selected by imm8 from xmm1 and xmm1/m128 to xmm1. |
Moves two of the four packed single-precision floating-point values from destination operand (first operand) into the low quadword of the destination operand; moves two of the four packed single-precision floating-point values in the source operand into to the high quadword of the destination operand (see Figure 3-17). The select operand (third operand) determines which values are moved to the destination operand.
The source operand can be an XXM register or a 128-bit memory location. The destination operand is an XMM register. The select operand is an 8-bit immediate: bits 0 and 1 select the value to be moved from the destination operand the low doubleword of the result, bits 2 and 3 select the value to be moved from the destination operand the second doubleword of the result, bits 4 and 5 select the value to be moved from the source operand the third doubleword of the result, and bits 6 and 7 select the value to be moved from the source operand the high doubleword of the result.
CASE (SELECT.[1-0]) OF
0: DEST[31-0] 
DEST[31-0];
1: DEST[31-0] DEST[63-32];
2: DEST[31-0] DEST[95-64];
3: DEST[31-0] DEST[127-96];
ESAC;
CASE (SELECT.[3-2]) OF
0: DEST[63-32] DEST[31-0];
1: DEST[63-32] DEST[63-32];
2: DEST[63-32] DEST[95-64];
3: DEST[63-32] DEST[127-96];
ESAC;
CASE (SELECT.[5-4]) OF
0: DEST[95-64] SRC[31-0];
1: DEST[95-64] SRC[63-32];
2: DEST[95-64] SRC[95-64];
3: DEST[95-64] SRC[127-96];
ESAC;
CASE (SELECT.[7-6]) OF
0: DEST[127-96] SRC[31-0];
1: DEST[127-96] SRC[63-32];
2: DEST[127-96] SRC[95-64];
3: DEST[127-96] SRC[127-96];
ESAC;
SHUFPS __m128 _mm_shuffle_ps(__m128 a, __m128 b, unsigned int imm8)
None.
#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0) - For an illegal address in the SS segment.
#PF(fault-code) - For a page fault.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment.
Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
Same exceptions as in Real Address Mode.
#PF(fault-code) - For a page fault.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.