Shifts (rotates) the bits of the first operand (destination operand)
the number of bit positions specified in the second operand (count operand)
and stores the result in the destination operand. The destination operand
can be a register or a memory location; the count operand is an unsigned
integer that can be an immediate or a value in the CL register. The processor
restricts the count to a number between 0 and 31 by masking all the bits
in the count operand except the 5 least-significant bits.
The rotate left (ROL) and rotate through carry left (RCL) instructions
shift all the bits toward more-significant bit positions, except for the
most-significant bit, which is rotated to the least-significant bit location
(see Figure 6-10 in the IA-32 Intel(R) Architecture Software Developer's Manual,
Volume 1). The rotate right (ROR) and rotate through carry right
(RCR) instructions shift all the bits toward less significant bit positions,
except for the least-significant bit, which is rotated to the most-significant
bit location (see Figure 6-10 in the IA-32 Intel(R) Architecture Software Developer's Manual,
Volume 1).
The RCL and RCR instructions include the CF flag in the rotation. The
RCL instruction shifts the CF flag into the least-significant bit and
shifts the most-significant bit into the CF flag (see Figure 6-10 in the
IA-32
Intel(R) Architecture Software Developer's Manual, Volume 1). The
RCR instruction shifts the CF flag into the most-significant bit and shifts
the least-significant bit into the CF flag (see Figure 6-10 in the IA-32
Intel(R) Architecture Software Developer's Manual, Volume 1). For
the ROL and ROR instructions, the original value of the CF flag is not
a part of the result, but the CF flag receives a copy of the bit that
was shifted from one end to the other.
The OF flag is defined only for the 1-bit rotates; it is undefined in
all other cases (except that a zero-bit rotate does nothing, that is affects
no flags). For left rotates, the OF flag is set to the exclusive OR of
the CF bit (after the rotate) and the most-significant bit of the result.
For right rotates, the OF flag is set to the exclusive OR of the two most-significant
bits of the result.
Intel(R) Architecture Compatibility
The 8086 does not mask the rotation count. However, all other Intel(R)
Architecture processors (starting with the Intel(R) 286 processor) do mask the rotation count to 5
bits, resulting in a maximum count of 31. This masking is done in all
operating modes (including the virtual-8086 mode) to reduce the maximum
execution time of the instructions.
Operation
(* RCL and RCR instructions *)
SIZE OperandSize
CASE (determine count) OF
SIZE 8: tempCOUNT
(COUNT AND 1FH)
MOD 9;
SIZE 16: tempCOUNT
(COUNT AND 1FH)
MOD 17;
SIZE 32: tempCOUNT
COUNT AND 1FH;
ESAC;
(* RCL instruction operation *)
WHILE (tempCOUNT
0)
DO
tempCF MSB(DEST);
DEST (DEST* 2) + CF;
CF tempCF;
tempCOUNT tempCOUNT
- 1;
OD;
ELIHW;
IF COUNT 1
THEN OF MSB(DEST)
XOR CF;
ELSE OF is undefined;
FI;
(* RCR instruction operation *)
IF COUNT 1
THEN OF MSB(DEST)
XOR CF;
ELSE OF is undefined;
FI;
WHILE (tempCOUNT
0)
DO
tempCF LSB(SRC);
DEST (DEST / 2) + (CF * 2SIZE);
CF tempCF;
tempCOUNT tempCOUNT
- 1;
OD;
(* ROL and ROR instructions *)
SIZE OperandSize
CASE (determine count) OF
SIZE 8: tempCOUNT
COUNT MOD 8;
SIZE 16: tempCOUNT
COUNT MOD 16;
SIZE 32: tempCOUNT
COUNT MOD 32;
ESAC;
(* ROL instruction operation *)
WHILE (tempCOUNT
0)
DO
tempCF MSB(DEST);
DEST (DEST* 2) + tempCF;
tempCOUNT tempCOUNT
- 1;
OD;
ELIHW;
CF LSB(DEST);
IF COUNT 1
THEN OF MSB(DEST)
XOR CF;
ELSE OF is undefined;
FI;
(* ROR instruction operation *)
WHILE (tempCOUNT
0)
DO
tempCF LSB(SRC);
DEST (DEST / 2) + (tempCF * 2SIZE);
tempCOUNT tempCOUNT
- 1;
OD;
ELIHW;
CF MSB(DEST);
IF COUNT 1
THEN OF MSB(DEST)
XOR MSB - 1(DEST);
ELSE OF is undefined;
FI;
Flags Affected
The CF flag contains the value of the bit shifted into it. The OF flag
is affected only for single-bit rotates (see "Description" above);
it is undefined for multi-bit rotates. The SF, ZF, AF, and PF flags are
not affected.
Protected Mode Exceptions
#GP(0) - If the source operand is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit. If the DS, ES, FS, or GS register contains a null segment
selector.
#SS(0) - If a memory operand effective address is outside the SS segment
limit.
#PF(fault-code) - If a page fault occurs.
#AC(0) - If alignment checking is enabled and an unaligned memory reference
is made while the current privilege level is 3.
Real-Address Mode Exceptions
#GP - If a memory operand effective address is outside the CS, DS, ES,
FS, or GS segment limit.
#SS - If a memory operand effective address is outside the SS segment
limit.
Virtual-8086 Mode Exceptions
#GP(0) - If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
#SS(0) - If a memory operand effective address is outside the SS segment
limit.
#PF(fault-code) - If a page fault occurs.
#AC(0) - If alignment checking is enabled
and an unaligned memory reference is made.
For details, see Volume 2A and Volume 2B of the Intel(R)
64 and IA-32 Intel Architecture Software Developer's Manual. For
the latest updates on the instruction set information, go to the
web site.
OperandSize
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