PSLLW/PSLLD/PSLLQ--Packed Shift Left Logical

Description

Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first operand) to the left by the number of bits specified in the count operand (second operand). As the bits in the data elements are shifted left, the empty low-order bits are cleared (set to 0). If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand is set to all 0s. (Figure 3-11 gives an example of shifting words in a 64-bit operand.)

Figure 3-11. PSLLW, PSLLD, and PSLLQ Instruction Operation

The destination operand may be an MMX™ technology register or an XMM register; the count operand can be either an MMX register or an 64-bit memory location, an XMM register or a 128-bit memory location, or an 8-bit immediate.

The PSLLW instruction shifts each of the words in the destination operand to the left by the number of bits specified in the count operand; the PSLLD instruction shifts each of the doublewords in the destination operand; and the PSLLQ instruction shifts the quadword (or quadwords) in the destination operand.

Operation

PSLLW instruction with 64-bit operand:
IF (COUNT > 15)
THEN
DEST[64..0] 0000000000000000H
ELSE
DEST[15..0] ZeroExtend(DEST[15..0] << COUNT);
* repeat shift operation for 2nd and 3rd words *;
DEST[63..48] ZeroExtend(DEST[63..48] << COUNT);
FI;

PSLLD instruction with 64-bit operand:
IF (COUNT > 31)
THEN
DEST[64..0] 0000000000000000H
ELSE
DEST[31..0] ZeroExtend(DEST[31..0] << COUNT);
DEST[63..32] ZeroExtend(DEST[63..32] << COUNT);
FI;

PSLLQ instruction with 64-bit operand:
IF (COUNT > 63)
THEN
DEST[64..0] 0000000000000000H
ELSE
DEST ZeroExtend(DEST << COUNT);
FI;

PSLLW instruction with 128-bit operand:
IF (COUNT > 15)
THEN
DEST[128..0] 00000000000000000000000000000000H
ELSE
DEST[15-0] ZeroExtend(DEST[15-0] << COUNT);
* repeat shift operation for 2nd through 7th words *;
DEST[127-112] ZeroExtend(DEST[127-112] << COUNT);
FI;

PSLLD instruction with 128-bit operand:
IF (COUNT > 31)
THEN
DEST[128..0] 00000000000000000000000000000000H
ELSE
DEST[31-0] ZeroExtend(DEST[31-0] << COUNT);
* repeat shift operation for 2nd and 3rd doublewords *;
DEST[127-96] ZeroExtend(DEST[127-96] << COUNT);
FI;

PSLLQ instruction with 128-bit operand:
IF (COUNT > 15)
THEN
DEST[128..0] 00000000000000000000000000000000H
ELSE
DEST[63-0] ZeroExtend(DEST[63-0] << COUNT);
DEST[127-64] ZeroExtend(DEST[127-64] << COUNT);
FI;

Intel(R) C++ Compiler Intrinsic Equivalents

PSLLW __m64 _mm_slli_pi16 (__m64 m, int count)

PSLLW __m64 _mm_sll_pi16(__m64 m, __m64 count)

PSLLW __m128i _mm_slli_pi16(__m64 m, int count)

PSLLW __m128i _mm_slli_pi16(__m128i m, __m128i count)

PSLLD __m64 _mm_slli_pi32(__m64 m, int count)

PSLLD __m64 _mm_sll_pi32(__m64 m, __m64 count)

PSLLD __m128i _mm_slli_epi32(__m128i m, int count)

PSLLD __m128i _mm_sll_epi32(__m128i m, __m128i count)

PSLLQ __m64 _mm_slli_si64(__m64 m, int count)

PSLLQ __m64 _mm_sll_si64(__m64 m, __m64 count)

PSLLQ __m128i _mm_slli_si64(__m128i m, int count)

PSLLQ __m128i _mm_sll_si64(__m128i m, __m128i count)

Flags Affected

None.

Protected Mode Exceptions

#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only.) If memory operand is not aligned on a 16-byte boundary, regardless of segment.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#UD - If EM in CR0 is set. (128-bit operations only.) If OSFXSR in CR4 is 0. (128-bit operations only.) If CPUID feature flag SSE-2 is 0.

#NM - If TS in CR0 is set.

#MF (64-bit operations only.) - If there is a pending x87 FPU exception.

#PF(fault-code) - If a page fault occurs.

#AC(0) (64-bit operations only.) - If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

#GP(0) (128-bit operations only.) - If memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.

#UD - If EM in CR0 is set. (128-bit operations only.) If OSFXSR in CR4 is 0. (128-bit operations only.) If CPUID feature flag SSE-2 is 0.

#NM - If TS in CR0 is set.

#MF (64-bit operations only.) - If there is a pending x87 FPU exception.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#PF(fault-code) - For a page fault.

#AC(0) (64-bit operations only.) - If alignment checking is enabled and an unaligned memory reference is made.

Numeric Exceptions

None.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.