PSHUFW--Packed Shuffle Words

Description

Shuffles the words in mm2/m64 using the imm8 operand to select which of the four words in mm2/mem will be placed in each of the words in MM1. Bits 1 and 0 of imm8 encode the source for destination word 0 (MM1[15-0]), bits 3 and 2 encode for word 1, bits 5 and 4 encode for word 2, and bits 7 and 6 encode for word 3 (MM1[63-48]). Similarly, the two-bit encoding represents which source word is to be used, e.g., a binary encoding of 10 indicates that source word 2 (MM2/Mem[47-32]) will be used.

Copies words from the source operand (second operand) and inserts them in the destination operand (first operand) at word locations selected with the order operand (third operand). This operation is similar to the operation used by the PSHUFD instruction, which is illustrated in Figure 3-10. For the PSHUFW instruction, each 2-bit field in the order operand selects the contents of one word location in the destination operand. The encodings of the order operand fields select words from the source operand to be copied to the destination operand.

The source operand can be an MMX™ technology register or a 64-bit memory location. The destination operand is an MMX register. The order operand is an 8-bit immediate.

Note that this instruction permits a word in the source operand to be copied to more than one word location in the destination operand.

Operation

DEST[15-0] (SRC >> (ORDER[1-0] * 16) )[15-0]
DEST[31-16] (SRC >> (ORDER[3-2] * 16) )[15-0]
DEST[47-32] (SRC >> (ORDER[5-4] * 16) )[15-0]
DEST[63-48] (SRC >> (ORDER[7-6] * 16) )[15-0]

Intel(R) C++ Compiler Intrinsic Equivalent

PSHUFW __m64 _mm_shuffle_pi16(__m64 a, int n)

Flags Affected

None.

Protected Mode Exceptions

#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#UD - If EM in CR0 is set.

#NM - If TS in CR0 is set.

#MF - If there is a pending x87 FPU exception.

#PF(fault-code) - If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

#GP(0) - If any part of the operand lies outside of the effective address space from 0 to FFFFH.

#UD - If EM in CR0 is set.

#NM - If TS in CR0 is set.

#MF - If there is a pending x87 FPU exception.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#PF(fault-code) - For a page fault.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made.

Numeric Exceptions

None.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.