PMOVMSKB--Move Byte Mask to General-Purpose Register

Description

Creates an 8-bit mask made up of the most significant bit of each byte of the source operand (second operand) and stores the result in the low byte or word of the destination operand (first operand). The source operand is an MMX™ technology or an XXM register; the destination operand is a general-purpose register.

Operation

PMOVMSKB instruction with 64-bit source operand:
r32[0] SRC[7];
r32[1] SRC[15];
* repeat operation for bytes 2 through 6;
r32[7] SRC[63];
r32[31-8] 000000H;

PMOVMSKB instruction with 128-bit source operand:
r32[0] SRC[7];
r32[1] SRC[15];
* repeat operation for bytes 2 through 14;
r32[15] SRC[127];
r32[31-16] 0000H;

Intel(R) C++ Compiler Intrinsic Equivalent

PMOVMSKB int_mm_movemask_pi8(__m64 a)

PMOVMSKB int _mm_movemask_epi8 ( __m128i a)

Flags Affected

None.

Protected Mode Exceptions

#UD 0 - If EM in CR0 is set. (128-bit operations only.) If OSFXSR in CR4 is 0. (128-bit operations only.) If CPUID feature flag SSE-2 is 0.

#NM - If TS in CR0 is set.

#MF (64-bit operations only.) - If there is a pending x87 FPU exception.

Real-Address Mode Exceptions

Same exceptions as in Protected Mode.

Virtual-8086 Mode Exceptions

Same exceptions as in Protected Mode.

Numeric Exceptions

None.

Numeric Exceptions

None.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.