DEST[31-0] *
SRC[31-0];DEST[63-32]
DEST[63-32]
* SRC[63-32];DEST[95-64]
DEST[95-64]
* SRC[95-64];DEST[127-96]
DEST[127-96]
* SRC[127-96];
Opcode |
Instruction |
Description |
|---|---|---|
|
0F 59 /r |
MULPS xmm1, xmm2/m128 |
Multiply packed single-precision floating-point values in xmm2/mem by xmm1. |
Performs a SIMD multiply of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the packed single-precision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Figure 10-5 in the IA-32 Intel(R) Architecture Software Developer's Manual, Volume 1 for an illustration of a SIMD single-precision floating-point operation.
DEST[31-0] DEST[31-0] *
SRC[31-0];
DEST[63-32] DEST[63-32]
* SRC[63-32];
DEST[95-64] DEST[95-64]
* SRC[95-64];
DEST[127-96] DEST[127-96]
* SRC[127-96];
MULPS __m128 _mm_mul_ps(__m128 a, __m128 b)
Overflow, Underflow, Invalid, Precision, Denormal.
#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments If memory operand is not aligned on a 16-byte boundary, regardless of segment .
#SS(0) - For an illegal address in the SS segment.
#PF(fault-code) - For a page fault.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment.
Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.
#NM - If TS in CR0 is set.
#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.
Same exceptions as in Real Address Mode.
#PF(fault-code) - For a page fault.
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.