MOVQ--Move Quadword

Description

Copies a quadword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be MMX™ technology registers, XMM registers, or 64-bit memory locations. This instruction can be used to move a between two MMX registers or between an MMX register and a 64-bit memory location, or to move data between two XMM registers or between an XMM register and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations.

When the source operand is an XMM register, the low quadword is moved; when the destination operand is an XMM register, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s.

Operation

MOVQ instruction when operating on MMX registers and memory locations:
DEST SRC;
MOVQ instruction when source and destination operands are XMM registers:
DEST[63-0] SRC[63-0];
MOVQ instruction when source operand is XMM register and destination
operand is memory location:
DEST SRC[63-0];
MOVQ instruction when source operand is memory location and destination
operand is XMM register:
DEST[63-0] SRC;
DEST[127-64] 0000000000000000H;

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0) - If the destination operand is in a nonwritable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#UD - If EM in CR0 is set. (XMM register operations only.) If OSFXSR in CR4 is 0. (XMM register operations only.) If CPUID feature flag SSE-2 is 0.

#NM - If TS in CR0 is set.

#MF (MMX register operations only.) - If there is a pending FPU exception.

#PF(fault-code) - If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

#GP - If any part of the operand lies outside of the effective address space from 0 to FFFFH.

#UD - If EM in CR0 is set. (XMM register operations only.) If OSFXSR in CR4 is 0. (XMM register operations only.) If CPUID feature flag SSE-2 is 0.

#NM - If TS in CR0 is set.

#MF (MMX register operations only.) - If there is a pending FPU exception.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode

#PF(fault-code) - If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.