MOVD--Move Doubleword

Description

Copies a doubleword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be general-purpose registers, MMX™ technology registers, XMM registers, or 32-bit memory locations. This instruction can be used to move a doubleword to and from the low doubleword an MMX register and a general-purpose register or a 32-bit memory location, or to and from the low doubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot be used to transfer data between MMX registers, between XMM registers, between general-purpose registers, or between memory locations.

When the destination operand is an MMX register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.

Operation

MOVD instruction when destination operand is MMX register:
DEST[31-0] SRC;
DEST[63-32] 00000000H;
MOVD instruction when destination operand is XMM register:
DEST[31-0] SRC;
DEST[127-32] 000000000000000000000000H;
MOVD instruction when source operand is MMX or XXM register:
DEST SRC[31-0];

Intel(R) C++ Compiler Intrinsic Equivalent

MOVD __m64 _mm_cvtsi32_si64 (int i ) MOVD int _mm_cvtsi64_si32 ( __m64m ) MOVD __m128i _mm_cvtsi32_si128 (int a) MOVD int _mm_cvtsi128_si32 ( __m128i a)

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0) - If the destination operand is in a nonwritable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#UD - If EM in CR0 is set. (XMM register operations only.) If OSFXSR in CR4 is 0. (XMM register operations only.) If CPUID feature flag SSE2 is 0.

#NM - If TS in CR0 is set.

#MF (MMX register operations only.) - If there is a pending FPU exception.

#PF(fault-code) If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

#GP - If any part of the operand lies outside of the effective address space from 0 to FFFFH.

#UD - If EM in CR0 is set. (XMM register operations only.) If OSFXSR in CR4 is 0. (XMM register operations only.) If CPUID feature flag SSE2 is 0.

#NM - If TS in CR0 is set.

#MF (MMX register operations only.) - If there is a pending FPU exception.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode

#PF(fault-code) - If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.