MAXPD--Maximum Packed Double-Precision Floating-Point Values

Description

Performs a SIMD compare of the packed double-precision floating-point values in the destination operand (first operand) and the source operand (second operand), and returns the maximum value for each pair of values to the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.

If the values being compared are both 0.0s, the value in the source operand is returned. If a value in source operand 2 is an SNaN, that SNaN is forwarded unchanged to the destination (that is, a QNaN version of the SNaN is not returned).

Note that if only one value is a NaN for this instruction, the source operand value (either NaN or valid floating-point value) is written to the result. This behavior allows compilers to use the MAXPD instruction for common C conditional constructs. If instead of this behavior, it is required that the NaN source operand be returned, the maximum functional can be emulated using a sequence of instructions: a comparison followed by AND, ANDN and OR.

Operation

DEST[63-0] IF (DEST[63-0] == SNaN) THEN SRC[63-0];
ELSE IF SRC[63-0] == SNaN) THEN SRC[63-0];
ELSE IF (DEST[63-0] > SRC[63-0])
THEN DEST[63-0]
ELSE SRC[63-0];
FI;
DEST[127-64] IF (DEST[127-64] == SNaN) THEN SRC[127-64];
ELSE IF SRC[127-64] == SNaN) THEN SRC[127-64];
ELSE IF (DEST[127-64] > SRC[63-0])
THEN DEST[127-64]
ELSE SRC[127-64];
FI;

Intel(R) C++ Compiler Intrinsic Equivalent

__m128d _mm_max_pd(__m128d a, __m128d b)

SIMD Floating-Point Exceptions

Invalid (including QNaN source operand), Denormal.

Protected Mode Exceptions

#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If memory operand is not aligned on a 16-byte boundary, regardless of segment.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#PF(fault-code) - For a page fault.

#NM - If TS in CR0 is set.

#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

Real-Address Mode Exceptions

#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment.

Interrupt 13 - If any part of the operand lies outside the effective address space from 0 to 0FFFFH.

#NM - If TS in CR0 is set.

#XM - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

#UD - If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#PF(fault-code) - For a page fault.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.