FXSAVE--Save x87 FPU, MMX™ Technology, Streaming SIMD Extensions, and Streaming SIMD Extensions 2 State

Description

The FXSAVE instruction writes the current state of the x87 FPU, MMX™ technology, Streaming SIMD Extensions, and Streaming SIMD Extensions 2 data, control, and status registers to the destination operand. The destination is a 512-byte memory location.

This instruction does not check for pending unmasked floating-point exceptions (similar to the operation of FNSAVE). Unlike the FSAVE/FNSAVE instructions, the processor retains the contents of the x87 FPU, MMX technology, Streaming SIMD Extension, and Streaming SIMD Extensions state in the processor after the state has been saved. The save data structure (see Layout of FXSAVE and FXRSTOR Memory Region) uses little-endian byte order as arranged in memory, with byte offset into row described by right column.

Three fields in the floating-point save area contain reserved bits that are not indicated in the table:

FOP: The lower 11-bits contain the opcode, upper 5-bits are reserved. IP & DP: 32-bit mode: 32-bit IP-offset. 16-bit mode: lower 16 bits are IP-offset and upper 16 bits are reserved.

The FXSAVE instruction is used when an operating system needs to perform a context switch or when an exception handler needs to use the floating-point, MMX technology, and Streaming SIMD Extension units. It cannot be used by an application program to pass a "clean" FP state to a procedure, since it retains the current state. An application must explicitly execute an FINIT instruction after FXSAVE to provide for this functionality.

All of the x87 FPU fields retain the same internal format as in FSAVE except for FTW.

Unlike FSAVE, FXSAVE saves only the FTW valid bits rather than the entire x87-FP FTW field. The FTW bits are saved in a non-TOS relative order, which means that FR0 is always saved first, followed by FR1, FR2 and so forth. As an example, if TOS=4 and only ST0, ST1 and ST2 are valid, FSAVE saves the FTW field in the following format:

ST3 ST2 ST1 ST0 ST7 ST6 ST5 ST4 (TOS=4) FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 11 xx xx xx 11 11 11 11

where xx is one of (00, 01, 10). (11) indicates an empty stack elements, and the 00, 01, and 10 indicate Valid, Zero, and Special, respectively.

In this example, FXSAVE would save the following vector:

FR7 FRits6 FR5 FR4 FR3 FR2 FR1 FR0 0 1 1 1 0 0 0 0

The FSAVE format for FTW can be recreated from the FTW valid bits and the stored 80-bit FP data (assuming the stored data was not the contents of MMX registers) using the following table:

The J-bit is defined to be the 1-bit binary integer to the left of the decimal place in the significand. The M-bit is defined to be the most significant bit of the fractional portion of the significand (i.e., the bit immediately to the right of the decimal place).

When the M- bit is the most significant bit of the fractional portion of the significand, it must be 0 if the fraction is all 0's.

If the FXSAVE instruction is immediately preceded by an FP instruction which does not use a memory operand, then the FXSAVE instruction does not write/update the DP field, in the FXSAVE image.

MXCSR holds the contents of the SIMD floating-point Control/Status Register. Refer to the LDMXCSR instruction for a full description of this field.

The fields XMM0-XMM7 contain the content of registers XMM0-XMM7 in exactly the same format as they exist in the registers.

The Streaming SIMD Extension fields in the save image (XMM0-XMM7 and MXCSR) may not be saved by the processor if the CR4.OSFXSR bit is not set. This CR4 bit must be set in order to enable execution of Streaming SIMD Extensions.

The destination m512byte is assumed to be aligned on a 16-byte boundary. If m512byte is not aligned on a 16-byte boundary, FXSAVE generates a general protection exception.

Operation

m512byte FP and MMX™ technology state and Streaming SIMD Extension state;

Numeric Exceptions

Invalid, Precision.

Protected Mode Exceptions

#GP(0) - For an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments. If memory operand is not aligned on a 16-byte boundary, regardless of segment.

#SS(0) - For an illegal address in the SS segment.

#PF (fault-code) - For a page fault.

#NM - If CR0.EM 1.

#NM - If TS bit in CR0 is set.

#UD - If instruction is preceded by a LOCK override prefix

#AC - For unaligned memory reference if the current privilege level is 3. If #AC is enabled (and CPL is 3), signaling of #AC is not guaranteed and may vary with implementation. In all implementations where #AC is not signaled, a general protection fault will instead be signaled. In addition, the width of the alignment check when #AC is enabled may also vary with implementation; for instance, for a given implementation, #AC might be signaled for a 2-byte misalignment, whereas #GP might be signaled for all other misalignments (4-, 8-, or 16-byte).

Real Address Mode Exceptions

#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment.

Interrupt 13 - If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.

#NM - If CR0.EM 1.

#NM - If TS bit in CR0 is set.

#UD - If instruction is preceded by a LOCK override prefix

Virtual 8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#AC - For unaligned memory reference if the current privilege level is 3.

#PF (fault-code) - For a page fault.

Comments

State saved with FXSAVE and restored with FRSTOR, and state saved with FSAVE and restored with FXRSTOR, will result in incorrect restoration of state in the processor. The address size prefix will have the usual effect on address calculation, but will have no effect on the format of the FXSAVE image.

The use of Repeat (F2H, F3H) and Operand-size (66H) prefixes with FXSAVE is reserved. Different processor implementations may handle these prefixes differently. Usage of these prefixes with FXSAVE risks incompatibility with future processors.

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.