FIST/FISTP--Store Integer

Opcode

Instruction

Description

DF /2

FIST m16int

Store ST(0) in m16int

DB /2

FIST m32int

Store ST(0) in m32int

DF /3

FISTP m16int

Store ST(0) in m16int and pop register stack

DB /3

FISTP m32int

Store ST(0) in m32int and pop register stack

DF /7

FISTP m64int

Store ST(0) in m64int and pop register stack

Description

The FIST instruction converts the value in the ST(0) register to a signed integer and stores the result in the destination operand. Values can be stored in word- or short-integer format. The destination operand specifies the address where the first byte of the destination value is to be stored.

The FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The FISTP instruction can also stores values in long-integer format.

The following table shows the results obtained when storing various classes of numbers in integer format.

ST(0)

DEST

- or Value Too Large for DEST Format

*

F ≤ −1

-I

-1 < -F < -0

**

-0

0

+0

0

+0 < +F < +1

**

F ≥ +1

+I

+ or Value Too Large for DEST Format

*

NaN

*

Note

If the source value is a non-integral value, it is rounded to an integer value, according to the rounding mode specified by the RC field of the FPU control word.

If the value being stored is too large for the destination format, is an , is a NaN, or is in an unsupported format and if the invalid-arithmetic-operand exception (#IA) is unmasked, an invalid-operation exception is generated and no value is stored in the destination operand. If the invalid-operation exception is masked, the integer indefinite value is stored in the destination operand.

Operation

DEST Integer(ST(0));
IF instruction FISTP
THEN
PopRegisterStack;
FI;

FPU Flags Affected

C1--Set to 0 if stack underflow occurred. Indicates rounding direction of if the inexact exception (#P) is generated: 0 not roundup; 1 roundup. Cleared to 0 otherwise.

C0, C2, C3 - Undefined.

Floating-Point Exceptions

#IS - Stack underflow occurred.

#IA - Source operand is too large for the destination format Source operand is a NaN value or unsupported format.

#P - Value cannot be represented exactly in destination format.

Protected Mode Exceptions

#GP(0) - If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#NM - EM or TS in CR0 is set.

#PF(fault-code) - If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

#GP - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS - If a memory operand effective address is outside the SS segment limit.

#NM - EM or TS in CR0 is set.

Virtual-8086 Mode Exceptions

#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#NM - EM or TS in CR0 is set.

#PF(fault-code) - If a page fault occurs.

#AC(0) - If alignment checking is enabled and an unaligned memory reference is made.

 

 

 

 

 

 

 


For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.