SIMD Floating-Point Exceptions

This topic lists additional exceptions that can occur when a Streaming SIMD Extensions and Streaming SIMD Extension 2 floating-point instruction is executed. All of these exception conditions result in a SIMD floating-point error exception (#XF, vector number 19) being generated. The following table associates each one-or two-letter mnemonic with the corresponding exception name. For a detailed description of these exceptions, refer to "Streaming SIMD Extensions and Streaming SIMD Extension 2 Exceptions", in Chapter 11 of the IA-32 Intel(R) Architecture Software Developer's Manual, Volume 1.

SIMD Floating-Point Exception Mnemonics and Names

Vector No.

Mnemonic

Name

Source

6

#UD

Invalid opcode

Memory access

6

#UD

Invalid opcode

Refer to Note 1 & Table 3-5

7

#NM

Device not available

Refer to Note 1 & Table 3-5

12

#SS

Stack exception

Memory access

13

#GP

General protection

Refer to Note 2

14

#PF

Page fault

Memory access

17

#AC

Alignment check

Refer to Note 3

19

#I

Invalid operation

Refer to Note 4

19

#Z

Divide-by-zero

Refer to Note 4

19

#D

Denormalized operand

Refer to Note 4

19

#O

Numeric overflow

Refer to Note 5

19

#U

Numeric underflow

Refer to Note 5

19

#P

Inexact result

Refer to Note 5

Note

  1. These are system exceptions. Table 3-5 lists the causes for Interrupt 6 and Interrupt 7 with Streaming SIMD Extensions.
  2. Executing a Streaming SIMD Extension with a misaligned 128-bit memory reference generates a general protection exception; a 128-bit reference within the stack segment, which is not aligned to a 16-byte boundary will also generate a GP fault, not a stack exception (SS). However, the MOVUPS instruction, which performs an unaligned 128-bit load or store, will not generate an exception for data that is not aligned to a 16-byte boundary.
  3. This type of alignment check is done for operands which are less than 128-bits in size: 32-bit scalar single and 16-bit/32-bit/64-bit integer MMX™ technology; the exception is the MOVUPS instruction, which performs a 128-bit unaligned load or store, is also covered by this alignment check. There are three conditions that must be true to enable #AC interrupt generation.
  4. Invalid, Divide-by-zero and Denormal exceptions are pre-computation exceptions, i.e., they are detected before any arithmetic operation occurs.
  5. Underflow, Overflow and Precision exceptions are post-computation exceptions.

Table 3-5. Streaming SIMD Extensions Faults (Interrupts 6 & 7)

CR0.EM

CR0.TS

CR4.OSFXSR

CPUID.XMM

Exception

1

-

-

-

#UD Interrupt 6

0

1

1

1

#NM Interrupt 7

-

-

0

-

#UD Interrupt 6

-

-

-

0

#UD Interrupt 6

 

 

 

 

 

 

 

 

 

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.