Real Address Mode Exceptions

This section lists the exceptions that can occur when the instruction is executed in real-address mode.

Exception Mnemonics, Names, and Vector Numbers

Vector No.

Mnemonic

Name

Source

0

#DE

Divide Error

DIV and IDIV instructions.

1

#DB

Debug

Any code or data reference.

3

#BP

Breakpoint

INT 3 instruction.

4

#OF

Overflow

INTO instruction.

5

#BR

BOUND Range Exceeded

BOUND instruction.

6

#UD

Invalid Opcode (Undefined Opcode)

UD2 instruction or reserved opcode. 1

7

#NM

Device Not Available (No Math Coprocessor)

Floating-point or WAIT/FWAIT instruction.

8

#DF

Double Fault

Any instruction that can generate an exception, an NMI, or an INTR.

10

#TS

Invalid TSS

Task switch or TSS access.

11

#NP

Segment Not Present

Loading segment registers or accessing system segments.

12

#SS

Stack Segment Fault

Stack operations and SS register loads.

13

#GP

General Protection

Any memory reference and other protection checks.

14

#PF

Page Fault

Any memory reference.

16

#MF

Floating-Point Error (Math Fault)

Floating-point or WAIT/FWAIT instruction.

17

#AC

Alignment Check

Any data reference in memory. 2

18

#MC

Machine Check

Model dependent. 3

19

#XF

SIMD Floating-Point Numeric Error

Streaming SIMD Extensions. 4

Note

  1. The UD2 instruction was introduced in the Intel(R) Pentium(R) Pro processor.
  2. This exception was introduced in the Intel486™ processor.
  3. This exception was introduced in the Pentium processor and enhanced in the Pentium Pro processor.
  4. This exception was introduced in the Pentium III processor.

 

 

 

 

 

 

 

 

For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.