The primary opcode is 1, 2, or 3 bytes. An additional 3-bit opcode field is sometimes encoded in the ModR/M byte. Smaller encoding fields can be defined within the primary opcode. These fields define the direction of the operation, the size of displacements, the register encoding, condition codes, or sign extension. The encoding of fields in the opcode varies, depending on the class of operation.
The "Opcode" column gives the complete object code produced for each form of the instruction. When possible, the codes are given as hexadecimal bytes, in the same order in which they appear in memory. Definitions of entries other than hexadecimal bytes are as follows:
/digit--A digit between 0 and 7 indicates that the ModR/M byte of the instruction uses only the r/m (register or memory) operand. The reg field contains the digit that provides an extension to the instruction's opcode.
/r--Indicates that the ModR/M byte of the instruction contains both a register operand and an r/m operand.
cb, cw, cd, cp--A 1-byte (cb), 2-byte (cw), 4-byte (cd), or 6-byte (cp) value following the opcode that is used to specify a code offset and possibly a new value for the code segment register.
ib, iw, id--A 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand to the instruction that follows the opcode, ModR/M bytes or scale-indexing bytes. The opcode determines if the operand is a signed value. All words and doublewords are given with the low-order byte first.
+rb, +rw, +rd--A register code, from 0 through 7, added to the hexadecimal byte given at the left of the plus sign to form a single opcode byte. The register codes are given in Table 3-1.
+i--A number used in floating-point instructions when one of the operands is ST(i) from the FPU register stack. The number i (which can range from 0 to 7) is added to the hexadecimal byte given at the left of the plus sign to form a single opcode byte.
|
|
rb |
|
|
rw |
|
|
rd |
|
|---|---|---|---|---|---|---|---|---|
|
AL |
= |
0 |
AX |
= |
0 |
EAX |
= |
0 |
|
CL |
= |
1 |
CX |
= |
1 |
ECX |
= |
1 |
|
DL |
= |
2 |
DX |
= |
2 |
EDX |
= |
2 |
|
BL |
= |
3 |
BX |
= |
3 |
EBX |
= |
3 |
|
|
rb |
|
|
rw |
|
|
rd |
|
|
AH |
= |
4 |
SP |
= |
4 |
ESP |
= |
4 |
|
CH |
= |
5 |
BP |
= |
5 |
EBP |
= |
5 |
|
DH |
= |
6 |
SI |
= |
6 |
ESI |
= |
6 |
|
BH |
= |
7 |
DI |
= |
7 |
EDI |
= |
7 |
For details, see Volume 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Architecture Software Developer's Manual. For the latest updates on the instruction set information, go to the web site.