Performance Counters on Intel(R) ProcessorsPerformance Counters on Intel(R) ProcessorsPerformance monitors allow processor events to be monitored by programmable counters or give an external notification (such as a pin or transaction) on the occurrence of an event. Monitors are useful for tuning application, operating system and system performance. Two sets of performance monitor registers are defined:
Performance Monitor Configuration (PMC) registers used to control the monitors
Performance Monitor Data (PMD) registers to provide data values from the monitors
The performance monitors can record performance values of instruction sets of either the IA-32 or IA-64 architecture application.
Intel(R) processors that belong to the P6 family of microarchitectures provide two 40-bit performance counters, allowing two types of events to be monitored simultaneously. These counters can either count events or measure duration. When counting events, a counter is incremented each time a specified event takes place or a specified number of events take place. When measuring duration, a counter counts the number of processor clocks that occur while a specified condition is true.
The Intel(R) Pentium(R) processor provides two 40-bit performance counters, which can be used either to count events or measure duration. Three Model Specific Registers (MSRs) support the performance-monitoring counters: the control and event select MSR (CESR) and the performance counter MSRs (CTR0 and CTR1). These registers can be read from and written to using the RDMSR and WRMSR instructions, respectively. They can be accessed using these instructions only when operating at privilege level 0. Each counter has as an associated external pin (PM0/BP0 and PM1/BP1), which can be used to indicate the state of the counter to external hardware.
The Intel(R) Pentium(R) 4 processor provides eighteen performance counters organized into nine pairs. The performance monitoring mechanism provided in the Pentium 4 processor is considerably different from that provided in the P6 family and Pentium processor. While the general concept of selecting, filtering, counting, and reading performance events through the WRMSR, RDMSR, and RDPMC instructions is unchanged, the setup mechanism and MSR layouts are different and incompatible with the P6 family and Pentium processor mechanisms. Also, the RDPMC instruction has been enhanced to read the additional performance counters provided in the Pentium 4 processor and to allow faster reading of the counters.
The Intel(R) Itanium(R) processor includes a minimum of four performance counters which can be programmed to count processor events. These event counts can be used to analyze both hardware and software performance. The performance counters of Itanium processors can be configured to generate a counter overflow interrupt. This interrupt can be used for both event and time-based sampling. Performance monitor interrupts can be used to create a profile of frequently occurring instruction pointers (IP) and this is the data that is displayed in the Hotspot view.