This event counts the number of instructions with a length changing prefix (LCP). Instructions with LCP change their length based on the existence of these prefixes:
operand-size prefix (0x66)
address size prefix (0x67).
For example, the following instruction encoded as (35 FF FF 00 00):
xor eax,0xffff
While the following instruction is encoded as (66 35 FF FF) and has a different size (the instruction size calculation does not include the 0x66 prefix):
xor ax,0xffff
The Intel(R) Pentium(R) M Processor instruction length decoder can not decode the length of a LCP instruction in one cycle, and therefore a slow decode chain starts for this instruction, which takes an additional five cycles to decode.
Recommendation: Avoid using instructions with immediate values which require a length changing prefix. Most common scenario for those is 16-bit immediate in 32-bit code.
You can use the VTune analyzer to count the number of slow decoder activations by using the LCP stall event.