FDIV/FLDCW Instructions

fdiv/fldcw_Stall indicates a penalty condition.

The floating-point instruction for which fdiv/fldcw_Stall is issued cannot begin executing until the previous FDIV or FLDCW instruction finishes executing its latency clocks. No other floating-point instruction can execute while FDIV or FLDCW executes.

Tip

Follow these guidelines to prevent the penalty condition:

Example:

Original

Cycle

Optimized

Cycle

1. fdiv DWORD PTR [ebp-4] 2. fadd st(0), st(1) 3. mov eax, 1 4. mov ebx, 1 5. mov ecx, 1

1 39 40 41 42

1. fdiv DWORD PTR [ebp-4] 3. mov eax, 1 4. mov ebx, 1 5. mov ecx, 1 2. fadd st(0), st(1)

1 2 3 4 39

No other floating-point instruction can execute while FDIV executes. Therefore, Instruction 2 stalls 38 cycles until FDIV finishes executing.
Total execution time: 42 cycles

The code is reorganized so that integer instructions execute in parallel to FDIV.
Total execution time: 39 cycles

Floating-point Penalties

Affected Processors