Trace Cache Misses

Trace cache misses occurred while in deliver mode, causing a significant negative performance impact. The working instruction set is too large to fit into the trace cache. The working instruction set should be targeted to fit into 1/2 of the trace cache. It is important to remember that the penalty for a second-level cache misses is much larger than for a trace cache miss.

For systems with the Hyper-Threading Technology enabled or multi-processor systems, the estimated impact represents the total processor time impact (added across all logical/physical processors on the system), and not the "wall-clock" time impact. Therefore, on a system with the Hyper-Threading Technology enabled or multi-processor system, it is quite possible to see an insight having an impact greater than the workload wall-clock run time. Note that on a UP system, processor time is the same as wall-clock time.

Counter dependencies:

This insight is dependent on the following performance counter function:

TC Miss Performance Impact = ((Trace Cache Misses*20)/Clockticks)*100
low value: 0.2
high value: 2

This insight is relevant when TC Miss Performance Impact is high.

Advice:

Try the Following Enhancements to Decrease Trace Cache Misses