Avoiding Cache Line Splits
For best performance, align data as follows:
- Align 8-bit data at any address
- Align 16-bit data to be contained within an aligned
four-byte word
- Align 32-bit data so that its base address is a multiple
of four
- Align 64-bit data so that its base address is a multiple
of eight
- Align 80-bit data so that its base address is a multiple
of sixteen
- Align 128-bit data so that its base address is a
multiple of sixteen
See chapter 2 of the Intel(R) Pentium(R) 4 and Intel(R) Xeon(R) Processor
Optimization Manual for details.