MEM_LOAD_RETIRED

Event Code: 0xCB

Mask: See in table below.

Available counters: 0,1,2,3

Category: Precise Event Based Sampling Performance Tuning Events;

Definition: Precise Events for on socket load access breakdown

Event Name Extension	Mask	Definition	Description
L1D_HIT	0x01	Retired loads that hit the L1 data cache (Precise Event)	Counts the number of retired loads that hit the L1 data cache.
L2_HIT	0x02	Retired loads that hit the L2 cache (Precise Event)	Counts the number of retired loads that hit the L2 data cache.
LLC_UNSHARED_HIT	0x04	Retired loads that hit valid versions in the LLC cache (Precise Event)	Counts the number of retired loads that hit their own, unshared lines in the LLC cache.
OTHER_CORE_L2_HIT_HITM	0x08	Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)	Counts the number of retired loads that hit in a sibling core's L2 (on die core). Since the LLC is inclusive of all cores on the package, this is an LLC hit. This counts both clean and modified hits.
LLC_MISS	0x10	Retired loads that miss the LLC cache (Precise Event)	Counts the number of retired loads that miss the LLC cache. The load was satisfied by a remote socket, local memory or an IOH.
HIT_LFB	0x40	Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)	Counts the number of retired loads that miss the L1D and the address is located in an allocated line fill buffer and will soon be committed to cache. This is counting secondary L1D misses.
DTLB_MISS	0x80	Retired loads that miss the DTLB (Precise Event)	Counts the number of retired loads that missed the DTLB. The DTLB miss is not counted if the load operation causes a fault. This event counts loads from cacheable memory only. The event does not count loads by software prefetches.