L2_RQSTS

Event Code: 0x24

Mask: See in table below.

Available counters: 0,1,2,3

Category: L2 Cache Performance Tuning Events;

Definition: L2 access request breakdown by instructions, loads, RFO, L2 HW Prefetch vs all, hit and miss

Event Name Extension	Mask	Definition	Description
LD_HIT	0x01	L2 load hits	Counts number of loads that hit the L2 cache. L2 loads include both L1D demand misses as well as L1D prefetches. L2 loads can be rejected for various reasions. Only non rejected loads are counted.
LD_MISS	0x02	L2 load misses	Counts the number of loads that miss the L2 cache. L2 loads include both L1D demand misses as well as L1D prefetches.
LOADS	0x03	L2 requests	Counts all L2 load requests. L2 loads include both L1D demand misses as well as L1D prefetches.
RFO_HIT	0x04	L2 RFO hits	Counts the number of store RFO requests that hit the L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. Count includes ItoM USWC memory requests, where the data is not fetched but the permission to write the line is requrired.
RFO_MISS	0x08	L2 RFO misses	Counts the number of store RFO requests that miss the L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
RFOS	0x0C	L2 RFO requests	Counts all L2 store RFO requests. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
IFETCH_HIT	0x10	L2 instruction fetch hits	Counts number of instruction fetches that hit the L2 cache. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches.
IFETCH_MISS	0x20	L2 instruction fetch misses	Counts number of instruction fetches that miss the L2 cache. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches.
IFETCHES	0x30	L2 instruction fetches	Counts all instruction fetches. L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches.
PREFETCH_HIT	0x40	L2 prefetch hits	Counts L2 prefetch hits for both code and data.
PREFETCH_MISS	0x80	L2 prefetch misses	Counts L2 prefetch misses for both code and data.
MISS	0xAA	All L2 misses	Counts all L2 misses for both code and data.
PREFETCHES	0xC0	All L2 prefetches	Counts all L2 prefetches for both code and data.
REFERENCES	0xFF	All L2 requests	Counts all L2 requests for both code and data.