About L1 Data Cache and DTLB Events

This group contains events that monitor the L1 data cache and the DTLB.

 

Symbol Name

Event Code

Description

CMP_SNOOP

0x78

L1 data cache is snooped by other core.

DTLB_MISSES.ANY

0x08

Memory accesses that missed the DTLB.

DTLB_MISSES.L0_MISS_LD

0x08

L0 DTLB misses due to load operations.

DTLB_MISSES.MISS_LD

0x08

DTLB misses due to load operations.

DTLB_MISSES.MISS_ST

0x08

DTLB misses due to store operations.

L1D_ALL_CACHE_REF

0x43

L1 Data cacheable reads and writes.

L1D_ALL_REF

0x43

All references to the L1 data cache.

L1D_CACHE_LD

0x40

L1 cacheable data reads.

L1D_CACHE_LOCK

0x42

L1 data cacheable locked reads

L1D_CACHE_LOCK_DURATION

0x42

Duration of L1 data cacheable locked operation.

L1D_CACHE_ST

0x41

L1 cacheable data writes.

L1D_M_EVICT

0x47

Modified cache lines evicted from the L1 data cache.

L1D_M_REPL

0x46

Modified cache lines allocated in the L1 data cache.

L1D_PEND_MISS

0x48

Total number of outstanding L1 data cache misses at any cycle.

L1D_PREFETCH.REQUESTS

0x4E

L1 data cache prefetch requests

L1D_REPL

0x45

Cache lines allocated in the L1 data cache.

L1D_SPLIT.LOADS

0x49

Cache line split loads from the L1 data cache.

L1D_SPLIT.STORES

0x49

Cache line split stores to the L1 data cache.

LOAD_BLOCK.L1D

0x03

Loads blocked by the L1 data cache.

LOAD_BLOCK.OVERLAP_STORE

0x03

Loads that partially overlap an earlier store, or 4K aliased with a previous store.

LOAD_BLOCK.STA

0x03

Loads blocked by a preceding store with unknown address.

LOAD_BLOCK.STD

0x03

Loads blocked by a preceding store with unknown data.

LOAD_BLOCK.UNTIL_RETIRE

0x03

Loads blocked until retirement.

MEMORY_DISAMBIGUATION.RESET

0x09

Memory disambiguation reset cycles.

MEMORY_DISAMBIGUATION.SUCCESS

0x09

Number of loads that were successfully disambiguated

MEM_LOAD_RETIRED.DTLB_MISS

0xCB

Retired loads that miss the DTLB (precise event).

MEM_LOAD_RETIRED.L1D_LINE_MISS

0xCB

L1 data cache line missed by retired loads (precise event).

MEM_LOAD_RETIRED.L1D_MISS

0xCB

Retired loads that miss the L1 data cache (precise event).

PAGE_WALKS.COUNT

0x0C

Number of page-walks executed.

PAGE_WALKS.CYCLES

0x0C

Duration of page-walks in core cycles

RESOURCE_STALLS.LD_ST

0xDC

Cycles during which the pipeline has exceeded load or store limit or waiting to commit all stores.

SB_DRAIN_CYCLES

0x04

Cycles while stores are blocked due to store buffer drain.

SEGMENT_REG_LOADS

0x06

Number of segment register loads.

STORE_BLOCK.ORDER

0x04

Cycles while store is waiting for a preceding store to be globally observed.

STORE_BLOCK.SNOOP

0x04

A store is blocked due to a conflict with an external or internal snoop.