mov cr
Format
(qp)movr 1 = cr 3 from_form M33
(qp)movcr 3 = r2 to_form M32
The source operand is copied to the destination register.
For the from_form, the control register specified by cr3 is read and the value copied into GR r1 .
For the to_form, GR r2 is read and the value copied into CR cr3.
Control registers can only be accessed at the most privileged level. Reading or writing an interruption control register (CR16-CR25), when the PSR.ic bit is one, will result in an Illegal Operation fault.
Operation
if (PR[qp]) {
if (is_reserved_reg(CR_TYPE, cr 3 )
|| to_form && is_read_only_reg(CR_TYPE, cr 3 )
|| PSR.ic && is_interruption_cr(cr 3 ))
{
illegal_operation_fault();
}
if (from_form)
check_target_register(r 1 );
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (from_form) {
if (cr 3 == IVR)
check_interrupt_request();
if (cr 3 == ITIR)
GR[r 1 ] = impl_itir_cwi_mask(CR[ITIR]);
else
GR[r 1 ] = CR[cr 3 ];
GR[r 1 ].nat = 0;
} else { // to_form
if (GR[r 2 ].nat)
register_nat_consumption_fault(0);
if (is_reserved_field(CR_TYPE, cr 3 , GR[r 2 ]))
reserved_register_field_fault();
if (cr 3 == EOI)
end_of_interrupt();
tmp_val = ignored_field_mask(CR_TYPE, cr 3 , GR[r 2 ]);
CR[cr 3 ] = tmp_val;
if (cr 3 == IIPA)
last_IP = tmp_val;
}
}
Illegal Operation fault
Register NaT Consumption fault
Privileged Operation fault
Reserved Register/Field fault
Serialization
Reads of control registers reflect the results of all prior instruction groups and interruptions.
In general, writes to control registers do not immediately affect subsequent instructions. Software must issue a serialize operation before a dependent instruction uses a modified resource. Control register writes are not implicitly synchronized with a corresponding control register read and requires data serialization.
For details, see Volume 3: Instruction Set Reference of the Intel(R) Itanium(R) Architecture Software Developer's Manual . For the latest updates on the instruction set information, go to the web site.