Load Register Stack Instruction

loadrs

Operation Font Conventions

Format

loadrs M25

Description

This instruction ensures that a specified number of bytes (registers values and/or NaT collections) below the current BSP have been loaded from the backing store into the stacked general registers. The loaded registers are placed into the dirty partition of the register stack. All other stacked general registers are marked as invalid, without being saved to the backing store.

The number of bytes to be loaded is specified in a sub-field of the RSC application register (RSC.loadrs). Backing store addresses are always 8-byte aligned, and therefore the low order 3 bits of the loadrs field (RSC.loadrs{2:0}) are ignored. This instruction can be used to invalidate all stacked registers outside the current frame, by setting RSC.loadrs to zero.

This instruction will fault with an Illegal Operation fault under any of the following conditions:

• The RSE is not in enforced lazy mode (RSC.mode is non-zero).

• CFM.sof and RSC.loadrs are both non-zero.

• An attempt is made to load up more registers than are available in the physical stacked register file.

This instruction must be the first instruction in an instruction group and must either be in instruction slot 0 or in instruction slot 1 of a template having a stop after slot 0; otherwise, the results are undefined. This instruction cannot be predicated.

• Illegal Operation fault
• Data NaT Page Consumption fault
• Unimplemented Data Address fault
• Data Key Miss fault
• Data Nested TLB fault
• Data Key Permission fault
• Alternate Data TLB fault
• Data Access Rights fault
• VHPT Data fault Data Access Bit fault
• Data TLB fault Data Debug fault
• Data Page Not Present fault

For details, see Volume 3: Instruction Set Reference of the Intel(R) Itanium(R) Architecture Software Developer's Manual . For the latest updates on the instruction set information, go to the web site.