srlz
Instruction Type M
Format
(qp) srlz.i instruction_form
(qp) srlz.d data_form
Description
Instruction serialization (srlz.i) ensures:
prior modifications to processor register resources that affect fetching of subsequent instruction groups are observed,
prior modifications to processor register resources that affect subsequent execution or data memory accesses are observed,
prior memory synchronization (sync.i) operations have taken effect on the local processor instruction cache,
subsequent instruction group fetches are re-initiated after srlz.i completes.
The srlz.i instruction must be in an instruction group after the instruction group containing the operation that is to be serialized. Operations dependent on the serialization must be in an instruction group after the instruction group containing the srlz.i.
Data serialization (srlz.d) ensures:
prior modifications to processor register resources that affect subsequent execution or data memory accesses are observed.
The srlz.d instruction must be in an instruction group after the instruction group containing the operation that is to be serialized. Operations dependent on the serialization must follow the srlz.d, but they can be in the same instruction group as the srlz.d.
A srlz cannot be used to stall processor data memory references until prior data memory references, or memory fences are visible or ”accepted” by the external platform.
The following processor resources require a serialize to ensure side-effects are observed; CRs, PSR, DBRs, IBRs, PMDs, PMCs, PRs, PKRs, TRs and TCs.
For details, see Volume 3: Instruction Set Reference of the Intel(R) Itanium(R) Architecture Software Developer's Manual . For the latest updates on the instruction set information, go to the web site.