lfetch
Instruction Type M
Format
(qp) lfetch.lftype.lfhint [r3] no_base_update_form
(qp) lfetch.lftype.lfhint [r3], r2 reg_base_update_form
(qp) lfetch.lftype.lfhint [r3], imm9 imm_base_update_form
(qp) lfetch.lftype.excl.lfhint [r3] no_base_update_form, exclusive_form
(qp) lfetch.lftype.excl.lfhint [r3], r2 reg_base_update_form, exclusive_form
(qp) lfetch.lftype.excl.lfhint [r3], imm9 imm_base_update_form, exclusive_form
Description
The line containing the address specified by the value in GR r3 is moved to the highest level of the data memory hierarchy. The value of the lfhint modifier specifies the locality of the memory access.
The behavior of the memory read is also determined by the memory attribute associated with the accessed page. Line size is implementation dependent but must be a power of two greater than or equal to 32 bytes. In the exclusive form, the cache line is allowed to be marked in an exclusive state. This qualifier is used when the program expects soon to modify a location in that line. If the memory attribute for the page containing the line is not cacheable, then no reference is made.
The completer, lftype, specifies whether or not the instruction raises faults normally associated with a regular load.
In the base update forms, after being used to address memory, the value in GR r3 is incremented by either the sign extended value in imm9 (in the imm_base_update_form) or the value in GR r2 (in the reg_base_update_form). In the reg_base_update_form, if the NaT bit corresponding to GR r2 is set, then the NaT bit corresponding to GR r3 is set - no fault is raised.
In the reg_base_update_form and the imm_base_update_form, if the NaT bit corresponding to GR r3 is clear, then the address specified by the value in GR r3 after the post-increment acts as a hint to prefetch the indicated cache line. The prefetch uses the locality hints specified by lfhint. The prefetch hint does not affect program functionality, does not raise any faults, and may be ignored by the implementation.
In the no_base_update_form, the value in GR r3 is not modified and no implicit prefetch hint is implied.
If the NaT bit corresponding to GR r3 is set then the state of memory is not affected. In the reg_base_update_form and imm_base_update_form, the post increment of GR r3 is performed and prefetch is hinted as described above.
A faulting lfetch to an unimplemented address results in an Unimplemented Data Address fault. A non-faulting lfetch to an unimplemented address does not take the fault and will not issue a prefetch request, but, if specified, will perform a register post-increment.
lfetch instructions, like hardware prefetches, are not orderable operations, i.e., they have no order with respect to prior or subsequent memory operations.
For details, see Volume 3: Instruction Set Reference of the Intel(R) Itanium(R) Architecture Software Developer's Manual . For the latest updates on the instruction set information, go to the web site.